Spartan3AN - Roadmap

Hi,
I just got a newsletter stating the Spartan3AN being available now. While 
these Spartan3AN are market as "new non-volatile" FPGAs, this might (IMHO) 
be misleading. For my understanding "non-volatile" would mean no 
configuration on power-ON (as e.g. ACTEL AntiFuse) rather than Config-Eprom 
being integrated in FPGA chip's housing (being a separate die as well). 
Nevertheless this definitely is a nice appraoch, saving space and copper 
traces on PCB.
As always, as soon as the new chip is on market the question on next 
enhancements arises. Any truth in rumors stating next generation Spartan (or 
what it will be called) has integrated Analog-Digital Converters?

CU, Carlhermann Schlehaus 

I personally see the FPGAs following a road that leads them to looking a 
lot like microcontrollers but with FPGA fabric where the processor is.


---Matthew Hicks


> Hi,
> I just got a newsletter stating the Spartan3AN being available now.
> While
> these Spartan3AN are market as "new non-volatile" FPGAs, this might
> (IMHO)
> be misleading. For my understanding "non-volatile" would mean no
> configuration on power-ON (as e.g. ACTEL AntiFuse) rather than
> Config-Eprom
> being integrated in FPGA chip's housing (being a separate die as
> well).
> Nevertheless this definitely is a nice appraoch, saving space and
> copper
> traces on PCB.
> As always, as soon as the new chip is on market the question on next
> enhancements arises. Any truth in rumors stating next generation
> Spartan (or
> what it will be called) has integrated Analog-Digital Converters?
> CU, Carlhermann Schlehaus
> 

Without divulging any secrets (hell,I do not even work in that
division of Xilinx, so how would I know?):
The biggest problem in integrating an A/D converter is deciding on its
parameters.
Should it be a slow, high-precision sigma-delta type, or successive
approximation, or a fast flash converter? Single channel or multi-
channel?
The trouble is that these are irreversible decision. You cannot morph
a slow 12-bit converter into a fast 8-bit converter (like you do
easily in the digital domain).
So it's a battle of temperature sensors vs industrial control, vs
audio, vs video. Tough choices!
Note: Virtex5 has a multi-input 10+-bit A/D converter in every chip.
It's called System Monitor. It had problems in Virtex-4, so we
disabled it there, but it works perfectly in Virtex-5.
Peter Alfke, Xilinx Applications
===================
On Mar 7, 10:47 am, "news.t-online.de" <carlhermann.schleh...@t-
online.de> wrote:
> Hi,
> I just got a newsletter stating the Spartan3AN being available now. While
> these Spartan3AN are market as "new non-volatile" FPGAs, this might (IMHO)
> be misleading. For my understanding "non-volatile" would mean no
> configuration on power-ON (as e.g. ACTEL AntiFuse) rather than Config-Eprom
> being integrated in FPGA chip's housing (being a separate die as well).
> Nevertheless this definitely is a nice appraoch, saving space and copper
> traces on PCB.
> As always, as soon as the new chip is on market the question on next
> enhancements arises. Any truth in rumors stating next generation Spartan (or
> what it will be called) has integrated Analog-Digital Converters?
>
> CU, Carlhermann Schlehaus

news.t-online.de wrote:
> Hi,
> I just got a newsletter stating the Spartan3AN being available now. 
> While these Spartan3AN are market as "new non-volatile" FPGAs, this 
> might (IMHO) be misleading. For my understanding "non-volatile" would 
> mean no configuration on power-ON (as e.g. ACTEL AntiFuse) rather than 
> Config-Eprom being integrated in FPGA chip's housing (being a separate 
> die as well).

Most of the FPGA architectures I know of, all load the config : I'm not 
sure even anti-fuse devices have the fuses actually in the signal path.
(imagine the tpd cost, of those fuse-program circuits ! )

So, what we are really talking about, it the time taken to load the 
config. Some are largely parallel, some are parallel-serial, and some
are pure serial (3AN).

I see your point, and "loader included" might be more accurate than "new 
non-volatile", as that claim also implies a certain security level that
other "non-volatile" alternatives DO offer.

> Nevertheless this definitely is a nice appraoch, saving 
> space and copper traces on PCB.
> As always, as soon as the new chip is on market the question on next 
> enhancements arises. Any truth in rumors stating next generation Spartan 
> (or what it will be called) has integrated Analog-Digital Converters?

I thought ADCs were already in FPGAs, but targeting temperature and
Vcc verification tasks, not mUXd to Pins (die is likely to be rather
noise for that..? )

-jg

>
> I thought ADCs were already in FPGAs, but targeting temperature and
> Vcc verification tasks, not mUXd to Pins (die is likely to be rather
> noise for that..? )
>

Hi Jim,
The Virtex-5 is the first Xilinx device to support an ADC, and most
other FPGAs (and FPGA companies!) don't have integrated ADC's at all.
The Virtex-5 System Monitor solution has an ADC core (200K/s), with
internal voltage sensors (Vccint and VccAux), and Temperature, plus a
dedicated high bandwidth input channel, and 16 channels that are
optional digital or analog IO. So no valuable pins used, unless you
want to.

To answer your question on noise: noise performance is very good, due
to all input channels being fully differential (and there is support
for bipolar and unipolar signals on all input channels).
Also, due to the speed of the ADC, and to further suppress noise,
averaging can be turned on for every channel, while still maintaining
a high sample rate.

Other features include automatic sequencing of the channels, and
alarms are available to warn you if the internal sensors detect
dangerous voltage/temperature conditions.

For more info see:
http://www.xilinx.com/systemmonitor

Or UG192:
http://direct.xilinx.com/bvdocs/userguides/ug192.pdf

Plug in chipscope to a Virtex-5 FPGA and it will read back the
internal voltage / temperature sensors live on a nice graph for you!

Hope this helps
John

John McGrath wrote:

>>I thought ADCs were already in FPGAs, but targeting temperature and
>>Vcc verification tasks, not mUXd to Pins (die is likely to be rather
>>noise for that..? )
>>
> 
> 
> Hi Jim,
> The Virtex-5 is the first Xilinx device to support an ADC, and most
> other FPGAs (and FPGA companies!) don't have integrated ADC's at all.
> The Virtex-5 System Monitor solution has an ADC core (200K/s), with
> internal voltage sensors (Vccint and VccAux), and Temperature, plus a
> dedicated high bandwidth input channel, and 16 channels that are
> optional digital or analog IO. So no valuable pins used, unless you
> want to.
> 
> To answer your question on noise: noise performance is very good, due
> to all input channels being fully differential (and there is support
> for bipolar and unipolar signals on all input channels).
> Also, due to the speed of the ADC, and to further suppress noise,
> averaging can be turned on for every channel, while still maintaining
> a high sample rate.
> 
> Other features include automatic sequencing of the channels, and
> alarms are available to warn you if the internal sensors detect
> dangerous voltage/temperature conditions.
> 
> For more info see:
> http://www.xilinx.com/systemmonitor
> 
> Or UG192:
> http://direct.xilinx.com/bvdocs/userguides/ug192.pdf
> 
> Plug in chipscope to a Virtex-5 FPGA and it will read back the
> internal voltage / temperature sensors live on a nice graph for you!
> 
> Hope this helps

Thanks for the details - good to see it's nice and flexible.

Can you comment on the OP's question :
"Any truth in rumors stating next generation Spartan (or what it will be 
called) has integrated Analog-Digital Converters? "

- would seem likely, once a block is finally proven on a process, all 
the hard work is done.

-jg

Jim,

> Can you comment on the OP's question :
> "Any truth in rumors stating next generation Spartan (or what it will be
> called) has integrated Analog-Digital Converters? "
> 
> - would seem likely, once a block is finally proven on a process, all
> the hard work is done.

That is true.

If enough customers when surveyed answered that the "system monitor"
added value to their devices, then I am sure the block is under
consideration for inclusion.

The real difficulty is that this block consumes area which is wasted for
anyone who doesn't need it.

With the constraints on pricing for Spartan parts, cost is everything.

This also presumes that there will be a new Spartan part on 65nm, and
exactly how this is featured is not something we can discuss here.  Does
it favor lower static power at the cost of system speed?  Or, does it
have medium speed, and medium static power (and no one is happy)?

As you may be well aware, the ITRS roadmap has some serious issues:

http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm

and even more depressing:

http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197700884

Technology has slowed to a crawl:  three years between nodes is now the
optimistic prediction.  Speed is hardly faster, leakage is far worse,
dimensions can not be made smaller (unless you don't care about yield).
 The 'fast' train has hit the "foothills" and we need to do more than
just make everything smaller (and get speed, power, and cost
improvements).  We now have to consider what our customers need (wow,
what a concept!), and decide how we may be able to add value.

Triple oxide, strained silicon, strained Ge-Si, silicon on insulator,
multiple voltages, multiple Vt's for nmos and pmos:  the toybox is
empty.  We have no hi-K gate dielectric (yet).  How do we 'improve'?

Even Intel and AMD have completely revised their stories:  it is no
longer about clock speed but "multicore" and "multicore+graphics
processor."  I have heard at a conference someone ask the Intel
presenter "isn't where you are going where FPGAs have already been?"

Austin

Austin Lesea wrote:
<snip>

> As you may be well aware, the ITRS roadmap has some serious issues:
> 
> http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
> 
> and even more depressing:
> 
> http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197700884
> 
> Technology has slowed to a crawl:  three years between nodes is now the
> optimistic prediction.  Speed is hardly faster, leakage is far worse,
> dimensions can not be made smaller (unless you don't care about yield).
>  The 'fast' train has hit the "foothills" and we need to do more than
> just make everything smaller (and get speed, power, and cost
> improvements).  We now have to consider what our customers need (wow,
> what a concept!), and decide how we may be able to add value.
> 
> Triple oxide, strained silicon, strained Ge-Si, silicon on insulator,
> multiple voltages, multiple Vt's for nmos and pmos:  the toybox is
> empty.  We have no hi-K gate dielectric (yet).  How do we 'improve'?
> 
> Even Intel and AMD have completely revised their stories:  it is no
> longer about clock speed but "multicore" and "multicore+graphics
> processor."  I have heard at a conference someone ask the Intel
> presenter "isn't where you are going where FPGAs have already been?"

You are right, tho some milestones are pushed out, as they prove less
essential than some believed :
450mm wafers is one (if die sizes are not going up, why should wafers ? 
), and immersion is delayed by advances in masking

and then, other technolgies suddenly look closer

This in todays news :
http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=35MFW2NZDZ2VMQSNDLSCKHA?articleID=197800524

"..sample a 90-nm 128-Mbit phase change memory to customers in the first 
half of 2007. Mass production could begin before the end of 2007 the 
chip giant said."

I have to be impressed - remember, this is intel (!), and aren't those 
times lines quite similar to today's just-sampling FPGAs ....

So, I went looking for speed info, and found this

:However, he did say that PRAM's random read access latency is very 
:comparable to DRAM. "Phase change memory fundamentally has a very fast 
:read speed, and how the bandwidth is depends on how it's configured in 
:the actual end product," said Kimoto.

PRAM does not show in the foundries plans at moment, but a stacked die 
PRAM + FPGA, with wide access bus, would  be near term do-able : mainly
dependant on the FPGA volumes being large enough to interest the big 
memory players...

-jg

Jim,

As I said, how do we IC designers "add value?"  If the ITRS mad dash has
slowed to a crawl, other technologies might 'catch up' and actually
become useful.(!)

We used to complain that we didn't have time to mess with dram+logic (or
eprom+fpga:  put you favorite combination here) on the same device,
maybe now we do?

Austin

Hi,
as Peter already wrote, the difficulty of implementation of ADC is to decide 
what application is to be targeted. I also recognize the problems of 
high-speed, high precise and high bitwidth ADCs may be distorted by the 
noise on the digital chip. I think those ADCs would have to be separately 
powered and accuratley decoupled from the digital part of the FPGA. In case 
the ADCs are targeted for temperature and sytem internal voltage monitoring, 
they are normally not that high sophisticated ones (the measured parameters 
won't change that quick, nor is a 12bit precision necessary. Those ADC may 
be implementable easier, while for e.g. brushless motor controllers those 
ADC's performance may not meet the control loop requirements (phase current 
measurement precision and sample rate). In case these ADCs are attached as 
separate ICs, they are easily selectable to suit the intended application's 
requirement perfectly.
I was just curious for future trends re. more functions to be integrated in 
one FPGA "housing".

Greetings, Carlhermann