Introducing picosecond delay between two output signals

On Mar 8, 7:28 am, "axr0284" <axr0...@yahoo.com> wrote:
> Thanks for all the answers. I guess using an external component might
> be more appropriate in this case. We used to use the AD9501 but it's
> going obsolete thus the problem. Anyways I'll keep digging for a
> solution. Thanks,
> Amish


For all my 10ps programmable delay line applications, I just use the
On Semiconductor MC10EP195.

http://www.onsemi.com/PowerSolutions/product.do?id=MC10EP195

Just remember that while ps may be very small, they Hertz just as
much.

Regards,

John McCaskill
www.fastertechnology.com

axr0284 wrote:
> Thanks for all the answers. I guess using an external component might
> be more appropriate in this case. We used to use the AD9501 but it's
> going obsolete thus the problem. Anyways I'll keep digging for a
> solution. Thanks,
> Amish

I tried searching a bit but did not find anything that comes close... the nearest I have 
seen was a Maxim part that had 25ns jitter and was marketed as a "programmable delay line" 
instead of "programmable delay generator".

I am almost certain I have seen the AD9501 (or a similar old chip, if there is any) pop up 
in one or two threads here over the last year. With some luck, the people involved may 
still be around.

Ulrich,

Just go into any CMOS chip, and then immediately leave that chip.

That is 35 ps right there (a 74AHC04 for example).

If you use LVDS, and have perfect terminations, maybe it becomes 25 ps.

Call it a limitation of the technology of bulk CMOS.

If you do anything else, the number just gets bigger.

If you anything wrong, the number also gets bigger (bad bypassing, bad
SI, etc.)

Austin

On 7 Mar 2007 13:59:49 -0800, "axr0284" <axr0284@yahoo.com> wrote:

>Hi,
> I would like to know what are the common methods of introducing
>delays as low as 10ps between two outputs in an FPGA. I do not
>currently have a specific FPGA in mind. I am just looking for a
>general answer.

That sounds like 2mm of PCB trace to me.

- Brian

In article <1173304789.265305.168410@p10g2000cwp.googlegroups.com>, 
axr0284@yahoo.com says...
> Hi,
>  I would like to know what are the common methods of introducing
> delays as low as 10ps between two outputs in an FPGA.

Do it on the PC board? Depending on board material, a 10 ps delay 
translates to adding about 2 mm to a trace length.

A worked out example of the math: an FR-4 microstrip has a dielectric 
constant of about 3.4, giving a transission velocity of:

(3e8 m/s)/sqrt(3.4) = 1.63e8 m/s

Multiplying by 10 ps (1e-11) cancels the seconds, giving 1.63e-3 m, or 
1.63 millimeters.

Of course, you need to adjust the dielectric constant for the material 
you're using, or you can end up wrong by a fairly substantial margin.

-- 
    Later,
    Jerry.

The universe is a figment of its own imagination.

Your main problem is that the temperature and voltage variations that
you're going to get in the FPGA will by FAR outweight the 10ps you're
looking for.  To prove this to yourself, take a simple design and run
it through your place and route tools.  Then open up timing analyzer
and look at a path, any path at all.  But make sure to select the
option to give you both setup & hold paths.  This is best case and
worst cast.  Lowest voltage & highest temperature is your setup path
or worst case delay....  highest voltage and lowest temperature is
your best case delay or hold path.  I promise you those two numbers
will vary by more than 10ps for almost any route in your part.  Even
the virtex 5, which can give you a temp/voltage compensated output
delay (the virex 4 would give you an input dealy, but no output) only
has a delay resolution in the order of 75ps.  Anywho... if ya think
about it - 10ps is a 100GHz signal.... there's a reason FPGAs
currently max out in the 500MHz range.... the variations are just too
big over temp and voltage. That's also why FPGA designs are usually
synchronous designs and the level sensitive world is generally left to
ASICs.

That being said... you're going to have a hard time getting a reliable
10ps delay in any manner - even analog sorts of manners - unless
you're in a strictly controlled environment.... but good luck :)

-Paul


On Mar 7, 4:59 pm, "axr0284" <axr0...@yahoo.com> wrote:
> Hi,
>  I would like to know what are the common methods of introducing
> delays as low as 10ps between two outputs in an FPGA. I do not
> currently have a specific FPGA in mind. I am just looking for a
> general answer.
>
>  I know there are DCMs but this usually adds jitter and one needs to
> wait for the DCM output to phase lock before the signal is stable and
> it might take too long in our case. Basically I would want to power up
> a board and have the delay be set in as short a time as possible. I
> also need to minimise jitter to a minimum so that the two signals are
> NEVER high at the same time. Thanks for any answer.
> Amish