Hi all, I have created a peripheral and attached it to the OPB bus. This peripheral is composed of a controller and also BRAM block directly attached to it. There is no bus between the controller and the BRAM block. The BRAM block is a 32KB block which is composed of 16 RAMB16 primitives. I have synthesized the peripheral which happens with out a glitch and then generated the netlist followed by the bitstream generation. All this happens but then the design report does not show that the peripheral is using the RAMB16 primitive. Someone please tell me what is wrong here. Also is there any example code which could guide me about how to use RAMB16's. I am using XPS 8.2i and ISE 8.2i and a virtex-4 board. Thanks, Bhanu
Design report does not show BRAM usage
Started by ●March 11, 2007
Reply by ●March 11, 20072007-03-11
Bhanu Chandra <vbhanu@gmail.com> wrote:> Hi all,> I have created a peripheral and attached it to the OPB bus. This > peripheral is composed of a controller and also BRAM block directly > attached to it. There is no bus between the controller and the BRAM > block. The BRAM block is a 32KB block which is composed of 16 RAMB16 > primitives.> I have synthesized the peripheral which happens with out a glitch and > then generated the netlist followed by the bitstream generation. All > this happens but then the design report does not show that the > peripheral is using the RAMB16 primitive. Someone please tell me what > is wrong here.> Also is there any example code which could guide me about how to use > RAMB16's.> I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.Read the synthesis report with care. It looks like the all the blockram and the surrounding circuits were removed because the output of the circuit is not used or the input is perhaps stable. Some typo in the instantiation may cause this. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●March 12, 20072007-03-12
On Mar 11, 11:13 pm, Uwe Bonnes <b...@hertz.ikp.physik.tu- darmstadt.de> wrote:> Bhanu Chandra <vbh...@gmail.com> wrote: > > Hi all, > > I have created a peripheral and attached it to the OPB bus. This > > peripheral is composed of a controller and also BRAM block directly > > attached to it. There is no bus between the controller and the BRAM > > block. The BRAM block is a 32KB block which is composed of 16 RAMB16 > > primitives. > > I have synthesized the peripheral which happens with out a glitch and > > then generated the netlist followed by the bitstream generation. All > > this happens but then the design report does not show that the > > peripheral is using the RAMB16 primitive. Someone please tell me what > > is wrong here. > > Also is there any example code which could guide me about how to use > > RAMB16's. > > I am using XPS 8.2i and ISE 8.2i and a virtex-4 board. > > Read the synthesis report with care. It looks like the all the blockram and > the surrounding circuits were removed because the output of the circuit is > not used or the input is perhaps stable. Some typo in the instantiation may > cause this. > > Bye > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Could someone please share a sample code which instantiates the BRAM blocks? Thanks, Bhanu
Reply by ●March 12, 20072007-03-12
Bhanu Chandra <vbhanu@gmail.com> wrote:> Could someone please share a sample code which instantiates the BRAM > blocks?Here I use one block as 8/32 Bit: /* * Tie unused data/address High (ug331, p.155 * Readout data is in upper portion */ RAMB16_S9_S36 ram1( .DOA(scaler_dout), .DOB(scaler_read_data), .DOPA(), .DOPB(), .ADDRA({{3{1'b1}},byteaddress[7:0]}), .ADDRB({{2{1'b1}},scaler_addr}), .CLKA(clk), .CLKB(clk), .DIA({8{1'b1}}), .DIB(scaler_write_data), .DIPA(4'b1), .DIPB(4'b1), .ENA((address == `SCALER)), .ENB(scaler_ena), .SSRA(1'b0), .SSRB(scaler_rst_cycle), .WEA(1'b0), .WEB(scaler_wea) ); The 8-bit side only reads the ram -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●March 12, 20072007-03-12
This is what I have, please tell me if something seems wrong here.
RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1),
.DOB (DOB_CAC1),
.DOPA (DOPA_CAC1),
.DOPB (DOPB_CAC1),
.ADDRA (ADDRA_CAC1),
.ADDRB (ADDRB_CAC1),
.CLKA (Bus2IP_Clk),
.CLKB (Bus2IP_Clk),
.DIA (DIA_CAC1),
.DIB (DIB_CAC1),
.DIPA (DIPA_CAC1),
.DIPB (DIPB_CAC1),
.ENA (ENA_CAC1),
.ENB (ENB_CAC1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (WEA_CAC1),
.WEB (WEB_CAC1));
defparam CAC1.INIT_00 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
Thanks,
Bhanu
Uwe Bonnes wrote:
> Bhanu Chandra <vbhanu@gmail.com> wrote:
>
> > Could someone please share a sample code which instantiates the BRAM
> > blocks?
>
> Here I use one block as 8/32 Bit:
> /*
> * Tie unused data/address High (ug331, p.155
> * Readout data is in upper portion
> */
> RAMB16_S9_S36 ram1(
> .DOA(scaler_dout),
> .DOB(scaler_read_data),
> .DOPA(),
> .DOPB(),
> .ADDRA({{3{1'b1}},byteaddress[7:0]}),
> .ADDRB({{2{1'b1}},scaler_addr}),
> .CLKA(clk),
> .CLKB(clk),
> .DIA({8{1'b1}}),
> .DIB(scaler_write_data),
> .DIPA(4'b1),
> .DIPB(4'b1),
> .ENA((address == `SCALER)),
> .ENB(scaler_ena),
> .SSRA(1'b0),
> .SSRB(scaler_rst_cycle),
> .WEA(1'b0),
> .WEB(scaler_wea)
> );
>
> The 8-bit side only reads the ram
>
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●March 12, 20072007-03-12
This is what I have, please tell me if something seems wrong here since this is the code that does not make BRAM usage appear in the design report. RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1), .DOB (DOB_CAC1), .DOPA (DOPA_CAC1), .DOPB (DOPB_CAC1), .ADDRA (ADDRA_CAC1), .ADDRB (ADDRB_CAC1), .CLKA (Bus2IP_Clk), .CLKB (Bus2IP_Clk), .DIA (DIA_CAC1), .DIB (DIB_CAC1), .DIPA (DIPA_CAC1), .DIPB (DIPB_CAC1), .ENA (ENA_CAC1), .ENB (ENB_CAC1), .SSRA (1'b0), .SSRB (1'b0), .WEA (WEA_CAC1), .WEB (WEB_CAC1)); defparam CAC1.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; Thanks, Bhanu Uwe Bonnes wrote:> Bhanu Chandra <vbhanu@gmail.com> wrote: > > > Could someone please share a sample code which instantiates the BRAM > > blocks? > > Here I use one block as 8/32 Bit: > /* > * Tie unused data/address High (ug331, p.155 > * Readout data is in upper portion > */ > RAMB16_S9_S36 ram1( > .DOA(scaler_dout), > .DOB(scaler_read_data), > .DOPA(), > .DOPB(), > .ADDRA({{3{1'b1}},byteaddress[7:0]}), > .ADDRB({{2{1'b1}},scaler_addr}), > .CLKA(clk), > .CLKB(clk), > .DIA({8{1'b1}}), > .DIB(scaler_write_data), > .DIPA(4'b1), > .DIPB(4'b1), > .ENA((address == `SCALER)), > .ENB(scaler_ena), > .SSRA(1'b0), > .SSRB(scaler_rst_cycle), > .WEA(1'b0), > .WEB(scaler_wea) > ); > > The 8-bit side only reads the ram > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●March 12, 20072007-03-12
On Mar 12, 4:04 pm, "Bhanu Chandra" <vbh...@gmail.com> wrote:> This is what I have, please tell me if something seems wrong here > since this is the code that does not make BRAM usage appear in the > design report. > > RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1), > .DOB (DOB_CAC1), > .DOPA (DOPA_CAC1), > .DOPB (DOPB_CAC1), > .ADDRA (ADDRA_CAC1), > .ADDRB (ADDRB_CAC1), > .CLKA (Bus2IP_Clk), > .CLKB (Bus2IP_Clk), > .DIA (DIA_CAC1), > .DIB (DIB_CAC1), > .DIPA (DIPA_CAC1), > .DIPB (DIPB_CAC1), > .ENA (ENA_CAC1), > .ENB (ENB_CAC1), > .SSRA (1'b0), > .SSRB (1'b0), > .WEA (WEA_CAC1), > .WEB (WEB_CAC1)); > > defparam CAC1.INIT_00 = > 256'h0000000000000000000000000000000000000000000000000000000000000000; > > Thanks, > Bhanu > > Uwe Bonnes wrote: > > Bhanu Chandra <vbh...@gmail.com> wrote: > > > > Could someone please share a sample code which instantiates the BRAM > > > blocks? > > > Here I use one block as 8/32 Bit: > > /* > > * Tie unused data/address High (ug331, p.155 > > * Readout data is in upper portion > > */ > > RAMB16_S9_S36 ram1( > > .DOA(scaler_dout), > > .DOB(scaler_read_data), > > .DOPA(), > > .DOPB(), > > .ADDRA({{3{1'b1}},byteaddress[7:0]}), > > .ADDRB({{2{1'b1}},scaler_addr}), > > .CLKA(clk), > > .CLKB(clk), > > .DIA({8{1'b1}}), > > .DIB(scaler_write_data), > > .DIPA(4'b1), > > .DIPB(4'b1), > > .ENA((address == `SCALER)), > > .ENB(scaler_ena), > > .SSRA(1'b0), > > .SSRB(scaler_rst_cycle), > > .WEA(1'b0), > > .WEB(scaler_wea) > > ); > > > The 8-bit side only reads the ram > > > -- > > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Seems like this is not the issue. What happened is that I had created a .h file within which I was doing all the instantiation. Possible that it was not including the file? I am getting a little confused here, XPS does not seem to support include directive of verilog. Has anyone tried it? I have now included the instantiation also in the main user_logic file, it now fails to resolve a function. Please mention if someone has in the past experienced the same problems. Thanks, Bhanu
Reply by ●March 12, 20072007-03-12
Bhanu Chandra <vbhanu@gmail.com> wrote: ...> Seems like this is not the issue. What happened is that I had created > a .h file within which I was doing all the instantiation. Possible > that it was not including the file? I am getting a little confused > here, XPS does not seem to support include directive of verilog. Has > anyone tried it? I have now included the instantiation also in the > main user_logic file, it now fails to resolve a function. Please > mention if someone has in the past experienced the same problems.Make sure it gets included. The "Device utilization summary" after running XST should read: Selected Device : 3s200pq208-4 ... Number of BRAMs: 1 out of 12 8% ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●March 12, 20072007-03-12
On Mar 11, 7:23 am, "Bhanu Chandra" <vbh...@gmail.com> wrote:> Hi all, > > I have created a peripheral and attached it to the OPB bus. This > peripheral is composed of a controller and also BRAM block directly > attached to it. There is no bus between the controller and the BRAM > block. The BRAM block is a 32KB block which is composed of 16 RAMB16 > primitives. > > I have synthesized the peripheral which happens with out a glitch and > then generated the netlist followed by the bitstream generation. All > this happens but then the design report does not show that the > peripheral is using the RAMB16 primitive. Someone please tell me what > is wrong here. > > Also is there any example code which could guide me about how to use > RAMB16's. > > I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.Did you infer the BRAMs or did you instantiate them? If the former, carefully check your synthesis report. Unfortunately, the tools will give you a polite Info: if your code did not properly infer a BRAM. -a
Reply by ●March 12, 20072007-03-12
On Mar 12, 5:32 am, "Bhanu Chandra" <vbh...@gmail.com> wrote:> On Mar 12, 4:04 pm, "Bhanu Chandra" <vbh...@gmail.com> wrote: > > > > > This is what I have, please tell me if something seems wrong here > > since this is the code that does not make BRAM usage appear in the > > design report. > > > RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1), > > .DOB (DOB_CAC1), > > .DOPA (DOPA_CAC1), > > .DOPB (DOPB_CAC1), > > .ADDRA (ADDRA_CAC1), > > .ADDRB (ADDRB_CAC1), > > .CLKA (Bus2IP_Clk), > > .CLKB (Bus2IP_Clk), > > .DIA (DIA_CAC1), > > .DIB (DIB_CAC1), > > .DIPA (DIPA_CAC1), > > .DIPB (DIPB_CAC1), > > .ENA (ENA_CAC1), > > .ENB (ENB_CAC1), > > .SSRA (1'b0), > > .SSRB (1'b0), > > .WEA (WEA_CAC1), > > .WEB (WEB_CAC1)); > > > defparam CAC1.INIT_00 = > > 256'h0000000000000000000000000000000000000000000000000000000000000000; > > > Thanks, > > Bhanu > > > Uwe Bonnes wrote: > > > Bhanu Chandra <vbh...@gmail.com> wrote: > > > > > Could someone please share a sample code which instantiates the BRAM > > > > blocks? > > > > Here I use one block as 8/32 Bit: > > > /* > > > * Tie unused data/address High (ug331, p.155 > > > * Readout data is in upper portion > > > */ > > > RAMB16_S9_S36 ram1( > > > .DOA(scaler_dout), > > > .DOB(scaler_read_data), > > > .DOPA(), > > > .DOPB(), > > > .ADDRA({{3{1'b1}},byteaddress[7:0]}), > > > .ADDRB({{2{1'b1}},scaler_addr}), > > > .CLKA(clk), > > > .CLKB(clk), > > > .DIA({8{1'b1}}), > > > .DIB(scaler_write_data), > > > .DIPA(4'b1), > > > .DIPB(4'b1), > > > .ENA((address == `SCALER)), > > > .ENB(scaler_ena), > > > .SSRA(1'b0), > > > .SSRB(scaler_rst_cycle), > > > .WEA(1'b0), > > > .WEB(scaler_wea) > > > ); > > > > The 8-bit side only reads the ram > > > > -- > > > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > Seems like this is not the issue. What happened is that I had created > a .h file within which I was doing all the instantiation. Possible > that it was not including the file? I am getting a little confused > here, XPS does not seem to support include directive of verilog. Has > anyone tried it? I have now included the instantiation also in the > main user_logic file, it now fails to resolve a function. Please > mention if someone has in the past experienced the same problems. > > Thanks, > BhanuI have Verilog code that uses include files, and it works with ISE. I stopped using them quite a while back because EDK lacks a method to tell it where to look for include files, and ISE just assumes that they are in its working directory unless told other wise. Regards, John McCaskill www.fastertechnology.com
