hi every body , please please how to calculate the sum of an array ( for example an array of std_logic_vector(3 downto 0) ) thank you
sum of array
Started by ●March 13, 2007
Reply by ●March 13, 20072007-03-13
Add them together? Your problem is not clear. Do you have an array in memory that you need to cycle through the elements one-by-one through an accumulator? Do you have an array of registers that needs a sum through a simple adder tree? Do you need to add two arrays held in memory to get a third array? Please clarify the help you would like. "VHDL_HELP" <abaidik@gmail.com> wrote in message news:1173792287.141073.35720@t69g2000cwt.googlegroups.com...> hi every body , > > please please how to calculate the sum of an array ( for example an > array of std_logic_vector(3 downto 0) ) > > thank you
Reply by ●March 13, 20072007-03-13
On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote:> Add them together? > > Your problem is not clear. Do you have an array in memory that you need to > cycle through the elements one-by-one through an accumulator? Do you have > an array of registers that needs a sum through a simple adder tree? Do you > need to add two arrays held in memory to get a third array? > > Please clarify the help you would like. > > "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > > > hi every body , > > > please please how to calculate the sum of an array ( for example an > > array of std_logic_vector(3 downto 0) ) > > > thank youlibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity somme is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (3 downto 0); taille : in STD_LOGIC_VECTOR (2 downto 0); dout : out STD_LOGIC_VECTOR (3 downto 0) ); end somme; architecture Behavioral of somme is type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); signal s : tab; begin process(clk) begin if clk'event and clk ='1' then s(conv_integer(taille)) <= din; end if; end process; dout <= s(0) + s(1) + s(2) + s(3); end Behavioral; ------------------------------------------------------------------------------------------------------------------------------------------------ my problem is : a simple addition for elements of an array !!! this programm is correct into syntax but not synthetisable and it dont give me the results that i want please i m a beginner and i want a clear way to think how to make this simple addition thank you
Reply by ●March 13, 20072007-03-13
On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote:> Add them together? > > Your problem is not clear. Do you have an array in memory that you need to > cycle through the elements one-by-one through an accumulator? Do you have > an array of registers that needs a sum through a simple adder tree? Do you > need to add two arrays held in memory to get a third array? > > Please clarify the help you would like. > > "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > > > hi every body , > > > please please how to calculate the sum of an array ( for example an > > array of std_logic_vector(3 downto 0) ) > > > thank youlibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity somme is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (3 downto 0); taille : in STD_LOGIC_VECTOR (2 downto 0); -- clk_out : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0) ); end somme; architecture Behavioral of somme is type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); signal s : tab; begin process(clk) begin if clk'event and clk ='1' then s(conv_integer(taille)) <= din; end if; end process; dout <= s(0) + s(1) + s(2) + s(3); end Behavioral; ------------------------------------------------------------------------ it is correct on syntax but not sythetisable : it gives me as a reslt for dout : 4'hX
Reply by ●March 13, 20072007-03-13
On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote:> Add them together? > > Your problem is not clear. Do you have an array in memory that you need to > cycle through the elements one-by-one through an accumulator? Do you have > an array of registers that needs a sum through a simple adder tree? Do you > need to add two arrays held in memory to get a third array? > > Please clarify the help you would like. > > "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > > > hi every body , > > > please please how to calculate the sum of an array ( for example an > > array of std_logic_vector(3 downto 0) ) > > > thank youlibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity somme is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (3 downto 0); taille : in STD_LOGIC_VECTOR (2 downto 0); -- clk_out : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0) ); end somme; architecture Behavioral of somme is type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); signal s : tab; begin process(clk) begin if clk'event and clk ='1' then s(conv_integer(taille)) <= din; end if; end process; dout <= s(0) + s(1) + s(2) + s(3); end Behavioral; ------------------------------------------------------------------------ it is my program : correct on syntax but it dont give me results dout=4'hX that it is what i get on simulation
Reply by ●March 13, 20072007-03-13
"VHDL_HELP" <abaidik@gmail.com> wrote in message news:1173802687.701492.283170@64g2000cwx.googlegroups.com...> > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity somme is > Port ( clk : in STD_LOGIC; > din : in STD_LOGIC_VECTOR (3 downto 0); > taille : in STD_LOGIC_VECTOR (2 downto 0); > > dout : out STD_LOGIC_VECTOR (3 downto 0) > ); > end somme; > > architecture Behavioral of somme is > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > signal s : tab; > begin > process(clk) > begin > if clk'event and clk ='1' then > s(conv_integer(taille)) <= din; > end if; > end process; > dout <= s(0) + s(1) + s(2) + s(3); > end Behavioral; > > ------------------------------------------------------------------------------------------------------------------------------------------------ > my problem is : a simple addition for elements of an array !!! > this programm is correct into syntax but not synthetisable and it dont > give me the results that i want > please i m a beginner and i want a clear way to think how to make > this simple addition > thank youCould it be that you haven't yet written all four elements of the array in your simulation? At start, all four elements of s are 4'hX. All four elements have to be written in order to obtain a valid dout. I am curious about the (2 downto 0) on the taille input yet array(3 downto 0) on s. Are you trying to abbreviate: if( NOT taille(2) ) then s(conv_integer(taille(1 downto 0))) <= din; end if; or should taille be (1 downto 0) or should tab be array(7 downto 0) ?
Reply by ●March 13, 20072007-03-13
On 13 mar, 18:05, "John_H" <newsgr...@johnhandwork.com> wrote:> "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173802687.701492.283170@64g2000cwx.googlegroups.com... > > > > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity somme is > > Port ( clk : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (3 downto 0); > > taille : in STD_LOGIC_VECTOR (2 downto 0); > > > dout : out STD_LOGIC_VECTOR (3 downto 0) > > ); > > end somme; > > > architecture Behavioral of somme is > > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > > signal s : tab; > > begin > > process(clk) > > begin > > if clk'event and clk =3D'1' then > > s(conv_integer(taille)) <=3D din; > > end if; > > end process; > > dout <=3D s(0) + s(1) + s(2) + s(3); > > end Behavioral; > > > -----------------------------------------------------------------------=----=AD---------------------------------------------------------------------> > my problem is : a simple addition for elements of an array !!! > > this programm is correct into syntax but not synthetisable and it dont > > give me the results that i want > > please i m a beginner and i want a clear way to think how to make > > this simple addition > > thank you > > Could it be that you haven't yet written all four elements of the array in > your simulation? At start, all four elements of s are 4'hX. All four > elements have to be written in order to obtain a valid dout. I am curious > about the (2 downto 0) on the taille input yet array(3 downto 0) on s. A=re> you trying to abbreviate: > if( NOT taille(2) ) then > s(conv_integer(taille(1 downto 0))) <=3D din; > end if; > or should taille be (1 downto 0) or should tab be array(7 downto 0) ?for taille : i have to get an array of 4 elements so i need 2 bits to reference these elements ( the elements are represented with 4 bits ) no? that it is why i use taille isnt right?
Reply by ●March 13, 20072007-03-13
On 13 mar, 18:05, "John_H" <newsgr...@johnhandwork.com> wrote:> "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173802687.701492.283170@64g2000cwx.googlegroups.com... > > > > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity somme is > > Port ( clk : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (3 downto 0); > > taille : in STD_LOGIC_VECTOR (2 downto 0); > > > dout : out STD_LOGIC_VECTOR (3 downto 0) > > ); > > end somme; > > > architecture Behavioral of somme is > > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > > signal s : tab; > > begin > > process(clk) > > begin > > if clk'event and clk =3D'1' then > > s(conv_integer(taille)) <=3D din; > > end if; > > end process; > > dout <=3D s(0) + s(1) + s(2) + s(3); > > end Behavioral; > > > -----------------------------------------------------------------------=----=AD---------------------------------------------------------------------> > my problem is : a simple addition for elements of an array !!! > > this programm is correct into syntax but not synthetisable and it dont > > give me the results that i want > > please i m a beginner and i want a clear way to think how to make > > this simple addition > > thank you > > Could it be that you haven't yet written all four elements of the array in > your simulation? At start, all four elements of s are 4'hX. All four > elements have to be written in order to obtain a valid dout. I am curious > about the (2 downto 0) on the taille input yet array(3 downto 0) on s. A=re> you trying to abbreviate: > if( NOT taille(2) ) then > s(conv_integer(taille(1 downto 0))) <=3D din; > end if; > or should taille be (1 downto 0) or should tab be array(7 downto 0) ?for taille : i have to calculate the sum of 4 elements so i need 2 bits to reference the elements ( the elements are for 4 bits) no?
Reply by ●March 13, 20072007-03-13
My response isn't quoting properly so I'll top post to avoid confusion with the latest questions. I asked about taille because the input is dimensioned with three bits (2 downto 0) rather than 2 bits (1 downto 0). It's correct to use taille for an address but you're showing 3 bits to reference 4 elements. "VHDL_HELP" <abaidik@gmail.com> wrote in message news:1173806971.269800.43820@c51g2000cwc.googlegroups.com... On 13 mar, 18:05, "John_H" <newsgr...@johnhandwork.com> wrote:> > Could it be that you haven't yet written all four elements of the array in > your simulation? At start, all four elements of s are 4'hX. All four > elements have to be written in order to obtain a valid dout. I am curious > about the (2 downto 0) on the taille input yet array(3 downto 0) on s. > Are > you trying to abbreviate: > if( NOT taille(2) ) then > s(conv_integer(taille(1 downto 0))) <= din; > end if; > or should taille be (1 downto 0) or should tab be array(7 downto 0) ?for taille : i have to get an array of 4 elements so i need 2 bits to reference these elements ( the elements are represented with 4 bits ) no? that it is why i use taille isnt right?
Reply by ●March 14, 20072007-03-14
On Mar 13, 11:33 am, "VHDL_HELP" <abai...@gmail.com> wrote:> On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > > Add them together? > > > Your problem is not clear. Do you have an array in memory that you need to > > cycle through the elements one-by-one through an accumulator? Do you have > > an array of registers that needs a sum through a simple adder tree? Do you > > need to add two arrays held in memory to get a third array? > > > Please clarify the help you would like. > > > "VHDL_HELP" <abai...@gmail.com> wrote in message > > >news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > > > > hi every body , > > > > please please how to calculate the sum of an array ( for example an > > > array of std_logic_vector(3 downto 0) ) > > > > thank you > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity somme is > Port ( clk : in STD_LOGIC; > din : in STD_LOGIC_VECTOR (3 downto 0); > taille : in STD_LOGIC_VECTOR (2 downto 0); > -- clk_out : in STD_LOGIC; > dout : out STD_LOGIC_VECTOR (3 downto 0) > ); > end somme; > > architecture Behavioral of somme is > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > signal s : tab; > begin > process(clk) > begin > if clk'event and clk ='1' then > s(conv_integer(taille)) <= din; > end if; > end process; > dout <= s(0) + s(1) + s(2) + s(3); > end Behavioral; > > ------------------------------------------------------------------------ > it is my program : correct on syntax but it dont give me results > dout=4'hX > that it is what i get on simulationAs John_H pointed out, taille only needs to be 2 bits. In other words: taille : in STD_LOGIC_VECTOR (1 downto 0); As for your simulation problem, your test bench needs to supply the values to be loaded into your signal "s". Otherwise, you will see X for dout. -Dave Pollum
