sum of array

On 14 mar, 13:44, "Dave Pollum" <vze24...@verizon.net> wrote:
> On Mar 13, 11:33 am, "VHDL_HELP" <abai...@gmail.com> wrote:
>
>
>
> > On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote:
>
> > > Add them together?
>
> > > Your problem is not clear.  Do you have an array in memory that you need to
> > > cycle through the elements one-by-one through an accumulator?  Do you have
> > > an array of registers that needs a sum through a simple adder tree?  Do you
> > > need to add two arrays held in memory to get a third array?
>
> > > Please clarify the help you would like.
>
> > > "VHDL_HELP" <abai...@gmail.com> wrote in message
>
> > >news:1173792287.141073.35720@t69g2000cwt.googlegroups.com...
>
> > > > hi every body ,
>
> > > > please please how to calculate the sum of  an array  ( for example an
> > > > array of std_logic_vector(3 downto 0) )
>
> > > > thank you
>
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.STD_LOGIC_ARITH.ALL;
> > use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> > entity somme is
> >     Port ( clk : in  STD_LOGIC;
> >            din : in  STD_LOGIC_VECTOR (3 downto 0);
> >                           taille : in  STD_LOGIC_VECTOR (2 downto 0);
> >         --   clk_out : in  STD_LOGIC;
> >            dout : out  STD_LOGIC_VECTOR (3 downto 0)
> >                           );
> > end somme;
>
> > architecture Behavioral of somme is
> > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
> > signal s : tab;
> > begin
> >     process(clk)
> >       begin
> >         if clk'event and clk ='1' then
> >            s(conv_integer(taille)) <= din;
> >          end if;
> >     end process;
> >  dout <= s(0) + s(1) + s(2) + s(3);
> > end Behavioral;
>
> > ------------------------------------------------------------------------
> > it is my program : correct on syntax but it dont give me results
> > dout=4'hX
> > that it is what i get on simulation
>
> As John_H pointed out, taille only needs to be 2 bits.  In other
> words:
>   taille : in  STD_LOGIC_VECTOR (1 downto 0);
>
> As for your simulation problem, your test bench needs to supply the
> values to be loaded into your signal "s".  Otherwise, you will see X
> for dout.
>
> -Dave Pollum

i dont know it still the same problem

"VHDL_HELP" <abaidik@gmail.com> wrote in message 
news:1173890111.962169.307570@e65g2000hsc.googlegroups.com...
> On 14 mar, 13:44, "Dave Pollum" <vze24...@verizon.net> wrote:
>>
>> As John_H pointed out, taille only needs to be 2 bits.  In other
>> words:
>>   taille : in  STD_LOGIC_VECTOR (1 downto 0);
>>
>> As for your simulation problem, your test bench needs to supply the
>> values to be loaded into your signal "s".  Otherwise, you will see X
>> for dout.
>>
>> -Dave Pollum
>
> i dont know it still the same problem

So, tell us please: what does your simulation say the values of s(0), s(1), 
s(2), and s(3) are?

Troubleshooting involves breaking the problem down into smaller pieces, 
seeing if you can show the smaller pieces work or don't work.  If you have a 
smaller piece that works, you can now ignore it and only need to concentrate 
on the smaller piece that doesn't work.  You can cut that up into smaller 
pieces and isolate what works there. 

On 14 mar, 18:43, "John_H" <newsgr...@johnhandwork.com> wrote:
> "VHDL_HELP" <abai...@gmail.com> wrote in message
>
> news:1173890111.962169.307570@e65g2000hsc.googlegroups.com...
>
> > On 14 mar, 13:44, "Dave Pollum" <vze24...@verizon.net> wrote:
>
> >> As John_H pointed out, taille only needs to be 2 bits.  In other
> >> words:
> >>   taille : in  STD_LOGIC_VECTOR (1 downto 0);
>
> >> As for your simulation problem, your test bench needs to supply the
> >> values to be loaded into your signal "s".  Otherwise, you will see X
> >> for dout.
>
> >> -Dave Pollum
>
> > i dont know it still the same problem
>
> So, tell us please: what does your simulation say the values of s(0), s(1=
),
> s(2), and s(3) are?
>
> Troubleshooting involves breaking the problem down into smaller pieces,
> seeing if you can show the smaller pieces work or don't work.  If you hav=
e a
> smaller piece that works, you can now ignore it and only need to concentr=
ate
> on the smaller piece that doesn't work.  You can cut that up into smaller
> pieces and isolate what works there.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity somme is
    Port ( clk : in  STD_LOGIC;
	        reset : in STD_LOGIC;
                en : in  STD_LOGIC_VECTOR (3 downto 0);
	      clk_out : out STD_LOGIC;
               s : out  STD_LOGIC_VECTOR (3 downto 0));
end somme;

architecture Behavioral of somme is
TYPE tab is array(3 downto 0) of std_logic_vector(3 downto 0);
begin
 process
 VARIABLE t:tab;
   begin
 SEQ_LOOP: loop
  			wait until clk'event and clk =3D '1';-- Lecture  de premier =E9l=E9ment
du tableau 4 =E9l=E9ments
			exit SEQ_LOOP when reset =3D '1';
			clk_out <=3D '1';
         wait until clk'event and clk =3D '1';
			exit SEQ_LOOP when reset =3D '1';
			  t(0) :=3D en;

         wait until clk'event and clk =3D '1';-- Lecture  de deuxi=E8me
=E9l=E9ment du tableau 4 =E9l=E9ments
			exit SEQ_LOOP when reset =3D '1';
			clk_out <=3D '0';
         wait until clk'event and clk =3D '1';
			exit SEQ_LOOP when reset =3D '1';
			  t(1) :=3D en;

			wait until clk'event and clk =3D '1';-- Lecture  de troisi=E8me =E9l=E9m=
ent
du tableau 4 =E9l=E9ments
			exit SEQ_LOOP when reset =3D '1';
			clk_out <=3D '1';
         wait until clk'event and clk =3D '1';
			exit SEQ_LOOP when reset =3D '1';
			  t(2) :=3D en;

			wait until clk'event and clk =3D '1';-- Lecture  de quatri=E8me =E9l=E9m=
ent
du tableau 4 =E9l=E9ments
			exit SEQ_LOOP when reset =3D '1';
			clk_out <=3D '0';
         wait until clk'event and clk =3D '1';
			exit SEQ_LOOP when reset =3D '1';
			  t(3) :=3D en;
 end loop;
  s <=3D t(0) + t(1) + t(2) + t(3);
  end process;
end Behavioral;
---------------------------------------------------------------------------=
---------------------------------------------------------------------------=
--------------------------------------------------------------
this is my problem:
for the s(0) , s(1) , s(2) and s(3)  it gives me the numbers but for s
in simulation i have as a result 4'hU and 4'hX

"VHDL_HELP" <abaidik@gmail.com> wrote in message 
news:1174054292.325732.224840@y80g2000hsf.googlegroups.com...
<snip>
> -----------------------------
> this is my problem:
> for the s(0) , s(1) , s(2) and s(3)  it gives me the numbers but for s
> in simulation i have as a result 4'hU and 4'hX

If by s( ) you mean t( ) and all the t values are numbers according to your 
simulation and your resulting sum is 4'hU and 4'hX according to your 
simulation, it sounds like your simulator is broken.

VHDL gurus: is there *anything* that might go wrong with the addition given 
the libraries he has specified? 

On Fri, 16 Mar 2007 08:14:18 -0700, "John_H"
<newsgroup@johnhandwork.com> wrote:

>"VHDL_HELP" <abaidik@gmail.com> wrote in message 
>news:1174054292.325732.224840@y80g2000hsf.googlegroups.com...
><snip>
>> -----------------------------
>> this is my problem:
>> for the s(0) , s(1) , s(2) and s(3)  it gives me the numbers but for s
>> in simulation i have as a result 4'hU and 4'hX
>
>is there *anything* that might go wrong with the addition given 
>the libraries he has specified? 

Don't think so (although my dislike of STD_LOGIC_UNSIGNED 
is well enough known by now).

The problem is simpler:  SEQ_LOOP is an infinite loop
containing an implicit state machine.  The loop exits
only when reset is asserted.  If reset is held false, the
loop continues to iterate and the final assignment
is never executed, so 's' is never updated.

Could we please find the tutor (or book writer, or other
"authority") who is teaching beginners to use this
form of implicit state machine, and string him/her
up by a rope tied around some sensitive appendage?

It makes my blood boil so much that I'm willing to post
the (obvious, simple) code that works - assuming 
the use of NUMERIC_STD instead of STD_LOGIC_ARITH:

process (clk, reset)
  subtype T_chiffre is unsigned(3 downto 0);
  type T_tableau4x4 is array (0 to 3) of T_chiffre;
  variable lieu: unsigned(1 downto 0);
  variable t: T_tableau4x4;
  variable somme: T_chiffre;
begin
  if reset = '1' then
    -- remettre tout &#4294967295; zero
    lieu := "00";
    t := (others => (others => '0'));
    clk_out <= '0';
    s <= (others => '0');
  elsif rising_edge(clk) then
    -- faire le somme en ajoutant chaque numero memoris&#4294967295;
    somme := (others => '0');
    for i in t'range loop
      somme := somme + t(i);
    end loop;
    -- mettre le somme en m&#4294967295;moire "s"
    s <= somme;
    -- sauvegarder le num&#4294967295;ro prochain
    t(to_unsigned(lieu)) := en;
    -- ??? horloge /2 ???
    clk_out <= not lieu(0);
    -- pr&#4294967295;parer pour boucle prochain
    lieu := lieu + 1;
  end if;
end process;

Beware of arithmetic overflow.  Output gives the sum of the
most recently seen 4 values.  I have no idea why you want
clk_out.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On 16 mar, 16:53, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 16 Mar 2007 08:14:18 -0700, "John_H"
>
> <newsgr...@johnhandwork.com> wrote:
> >"VHDL_HELP" <abai...@gmail.com> wrote in message
> >news:1174054292.325732.224840@y80g2000hsf.googlegroups.com...
> ><snip>
> >> -----------------------------
> >> this is my problem:
> >> for the s(0) , s(1) , s(2) and s(3)  it gives me the numbers but for s
> >> in simulation i have as a result 4'hU and 4'hX
>
> >is there *anything* that might go wrong with the addition given
> >the libraries he has specified?
>
> Don't think so (although my dislike of STD_LOGIC_UNSIGNED
> is well enough known by now).
>
> The problem is simpler:  SEQ_LOOP is an infinite loop
> containing an implicit state machine.  The loop exits
> only when reset is asserted.  If reset is held false, the
> loop continues to iterate and the final assignment
> is never executed, so 's' is never updated.
>
> Could we please find the tutor (or book writer, or other
> "authority") who is teaching beginners to use this
> form of implicit state machine, and string him/her
> up by a rope tied around some sensitive appendage?
>
> It makes my blood boil so much that I'm willing to post
> the (obvious, simple) code that works - assuming
> the use of NUMERIC_STD instead of STD_LOGIC_ARITH:
>
> process (clk, reset)
>   subtype T_chiffre is unsigned(3 downto 0);
>   type T_tableau4x4 is array (0 to 3) of T_chiffre;
>   variable lieu: unsigned(1 downto 0);
>   variable t: T_tableau4x4;
>   variable somme: T_chiffre;
> begin
>   if reset =3D '1' then
>     -- remettre tout =E0 zero
>     lieu :=3D "00";
>     t :=3D (others =3D> (others =3D> '0'));
>     clk_out <=3D '0';
>     s <=3D (others =3D> '0');
>   elsif rising_edge(clk) then
>     -- faire le somme en ajoutant chaque numero memoris=E9
>     somme :=3D (others =3D> '0');
>     for i in t'range loop
>       somme :=3D somme + t(i);
>     end loop;
>     -- mettre le somme en m=E9moire "s"
>     s <=3D somme;
>     -- sauvegarder le num=E9ro prochain
>     t(to_unsigned(lieu)) :=3D en;
>     -- ??? horloge /2 ???
>     clk_out <=3D not lieu(0);
>     -- pr=E9parer pour boucle prochain
>     lieu :=3D lieu + 1;
>   end if;
> end process;
>
> Beware of arithmetic overflow.  Output gives the sum of the
> most recently seen 4 values.  I have no idea why you want
> clk_out.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

hi every body ,
i want to say thank you for all of u and this program can do the sum
that i want
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity som is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           en : in  STD_LOGIC_VECTOR (2 downto 0);
           clk_out : out  STD_LOGIC;
			  so : out  STD_LOGIC_VECTOR (3 downto 0);
           sor : out  STD_LOGIC_VECTOR (3 downto 0));
end som;

architecture Behavioral of som is
TYPE TAB IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
signal t:TAB;
SIGNAL s:STD_LOGIC_VECTOR (3 downto 0):=3D"0000";
begin
 process
   begin
     seq:loop
     wait until clk'event and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '1';
   t(0) <=3D en;

   wait until clk'event  and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '0';
   t(1) <=3D en;

   wait until clk'event and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '1';
   t(2) <=3D en;

   wait until clk'event  and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '0';
   t(3) <=3D en;
 ----- Mettre les =E9l=E9ments de tableau en sortie
       wait until clk'event and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '1';


   wait until clk'event and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '0';


   wait until clk'event and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '1';


   wait until clk'event and clk =3D '1';
     exit seq when reset =3D'1';
   clk_out <=3D '0';

   end loop;
	if reset =3D '1' then
	clk_out <=3D '0';
		s <=3D '0' & t(0) + t(1) +  t(2) + t(3);
      so <=3D s;
	end if;
 end process;
end Behavioral;

--- thank you again