Xilinx Netlist

Is there an easy way to get the Xilinx design manager to spit out a
netlist for a synthesized VHDL file?

Adam

On Mar 14, 9:11 am, "AdamE" <aelb...@cs.uml.edu> wrote:
> Is there an easy way to get the Xilinx design manager to spit out a
> netlist for a synthesized VHDL file?
>
> Adam

Do you want an EDIF netlist?  Xilinx tools generally create a .ngc
file which can be converted using ngc2edif from the command line.

On 2007-03-14, AdamE <aelbirt@cs.uml.edu> wrote:
> Is there an easy way to get the Xilinx design manager to spit out a
> netlist for a synthesized VHDL file?

It depends on what kind of netlist you want. As mentioned earlier it
is easy to get an EDIF netlist after the synthesis tool has run. But
something which could also be useful is an XDL netlist which you can
get after map or par has been executed.

(I guess I'm guilty of advocating XDL a lot lately but you can
do some really nifty tricks with it if you don't care about
portability that much :))

/Andreas

On 2007-03-14, Andreas Ehliar <ehliar@lysator.liu.se> wrote:
> It depends on what kind of netlist you want. As mentioned earlier it
> is easy to get an EDIF netlist after the synthesis tool has run. But
> something which could also be useful is an XDL netlist which you can
> get after map or par has been executed.

Ahem.. perhaps I should mention how to get such a netlist as well...

Use the xdl tool from the command line:

xdl -ncd2xdl yourdesign.ncd

/Andreas

On Mar 14, 7:59 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> On 2007-03-14, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
>
> > It depends on what kind of netlist you want. As mentioned earlier it
> > is easy to get an EDIF netlist after the synthesis tool has run. But
> > something which could also be useful is an XDL netlist which you can
> > get after map or par has been executed.
>
> Ahem.. perhaps I should mention how to get such a netlist as well...
>
> Use the xdl tool from the command line:
>
> xdl -ncd2xdl yourdesign.ncd
>
> /Andreas



What are some of the tricks you do with the xdl netlist?  Does it give
you a way to take a core through map and PAR and then use it as a
block box in a design that is going to go through map/PAR again?

I have been wanting to harden some cores that I use in all my EDK
designs, does this help any?  I already have several cores that I pull
in as black boxes and put area group constraints on.  It would be nice
to take those cores through PAR, and bring an already placed net list
in as a block box.

Regards,

John McCaskill
www.fastertechnology.com

On 2007-03-14, John McCaskill <junkmail@fastertechnology.com> wrote:
> What are some of the tricks you do with the xdl netlist?  Does it give
> you a way to take a core through map and PAR and then use it as a
> block box in a design that is going to go through map/PAR again?
>

One thing I've tried is to take a place and routed design and
then insert another core that peeked on some internal signals in
the first design. Think chipscope but using RS232 instead of JTAG
for communicating with the outside world. The flow I used basically
looks like this:


* Synthesize, map, and place and route your design to design.xdl

* Synthesize and map the rs232 based logic analyzer to analyzer.xdl

* Manually edit analyzer.xdl to remove stuff you are not interested in

* Manually merge analyzer.xdl into design.xdl

* convert xdl file to ncd and rerun par on it with exact guidemode

* Optional: Correct mistakes that xdl and par complained about :)


So it is not very streamlined I'm afraid :) But streamlining the
process is really only a matter of writing a perl script.  I
haven't tried this on any large design either so I don't know if
there are any gotchas...

Anyway, I would guess that there are quite a few possibilities here
for someone with a lot of time on their hands.


Another use of XDL which is less radical is to extract information
about the design. For a report I wrote some time ago I wrote an
XDL to Postscript converter in order to avoid bitmap graphic
of a floorplan :) And the xdlanalyze.pl script which I've mentioned
on comp.arch.fpga earlier.


> I have been wanting to harden some cores that I use in all my EDK
> designs, does this help any?  I already have several cores that I pull
> in as black boxes and put area group constraints on.  It would be nice
> to take those cores through PAR, and bring an already placed net list
> in as a block box.

As you've probably guessed by now I'm afraid that my experimentation
have not really been aimed at this... although I would be interested
in knowing about such a solution as well.

/Andreas

On 2007-03-15, Andreas Ehliar <ehliar@lysator.liu.se> wrote:
> * Synthesize, map, and place and route your design to design.xdl
>
> * Synthesize and map the rs232 based logic analyzer to analyzer.xdl
>
> * Manually edit analyzer.xdl to remove stuff you are not interested in
>
> * Manually merge analyzer.xdl into design.xdl

I forgot to include an important part here:
* Manually merge the constraints in design.pcf and analyze.pcf

/Andreas

On Mar 14, 7:36 pm, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> On 2007-03-15, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
>
> > * Synthesize, map, and place and route your design to design.xdl
>
> > * Synthesize and map the rs232 based logic analyzer to analyzer.xdl
>
> > * Manually edit analyzer.xdl to remove stuff you are not interested in
>
> > * Manually merge analyzer.xdl into design.xdl
>
> I forgot to include an important part here:
> * Manually merge the constraints in design.pcf and analyze.pcf
>
> /Andreas



Do you know if there is a way to get an xdl netlist back to an ngc
netlist?

What I would like to do is to take some of my IO cores that I use on
all of my designs and take them through PAR until I am happy with the
results and then be able to use them as hard macros from then on.

Regards,

John McCaskill
www.fastertechnology.com

On 2007-03-15, John McCaskill <junkmail@fastertechnology.com> wrote:
> Do you know if there is a way to get an xdl netlist back to an ngc
> netlist?

Not that I know of. Well, you can use netgen to convert a .ncd
design to vhdl or verilog and it might be possible to synthesize
this one. However it would not contain routing information.


> What I would like to do is to take some of my IO cores that I use on
> all of my designs and take them through PAR until I am happy with the
> results and then be able to use them as hard macros from then on.

I've found conflicting information about routing in hard macros,
some says the routing cannot be locked down like the following:
http://www.cse.ucsc.edu/classes/cmpe225/Fall01/hardmacro.html

And some say that it is possible, such as a hard bus macro that is
used in partial reconfiguration. Perhaps you could download such
a bus macro and see how they are constructed?


Mind you, I haven't tried this at all so I have no idea if it is
a good idea or not, but perhaps you could synthesize your I/O
macros one after one and place the result in one large XDL file which
you could then convert to NCD and use as a guide file for par.
It is a quite ugly solution though, there must be a better way.


But if you find an easy way to create such hard macros I'd be
interested as well :)

/Andreas

Sorry for the slow reply - winter colds stink ;)  I was actually
hoping to get a list of the synthesized logic equations prior to
conversion to the Xilinx primitives.  I was able to get an EDIF
netlist but that's a bit too far down the tool chain as what I want to
look at is the optimized Boolean logic.  Is that possible?  I seem to
recall that generic vendor tools like Synplify had the ability to
export such information prior to the selection of a target technology.

Adam


On Mar 15, 2:33 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> On 2007-03-15, John McCaskill <junkm...@fastertechnology.com> wrote:
>
> > Do you know if there is a way to get an xdl netlist back to an ngc
> > netlist?
>
> Not that I know of. Well, you can use netgen to convert a .ncd
> design to vhdl or verilog and it might be possible to synthesize
> this one. However it would not contain routing information.
>
> > What I would like to do is to take some of my IO cores that I use on
> > all of my designs and take them through PAR until I am happy with the
> > results and then be able to use them as hard macros from then on.
>
> I've found conflicting information about routing in hard macros,
> some says the routing cannot be locked down like the following:http://www.cse.ucsc.edu/classes/cmpe225/Fall01/hardmacro.html
>
> And some say that it is possible, such as a hard bus macro that is
> used in partial reconfiguration. Perhaps you could download such
> a bus macro and see how they are constructed?
>
> Mind you, I haven't tried this at all so I have no idea if it is
> a good idea or not, but perhaps you could synthesize your I/O
> macros one after one and place the result in one large XDL file which
> you could then convert to NCD and use as a guide file for par.
> It is a quite ugly solution though, there must be a better way.
>
> But if you find an easy way to create such hard macros I'd be
> interested as well :)
>
> /Andreas