Clearing fpga internal memory...

Hi, I have set of registers implemented as internal RAM blocks (in 
Cyclone FPGA). Is there any way to clear contents of this registers on 
demand (just like clear signal in D flip-flops)?

For answers thanks in advance.

"Yrjola" <yrjola@op.pl> wrote in message 
news:et8ugq$uaq$1@node4.news.atman.pl...
> Hi, I have set of registers implemented as internal RAM blocks (in Cyclone 
> FPGA). Is there any way to clear contents of this registers on demand 
> (just like clear signal in D flip-flops)?
>
> For answers thanks in advance.

Just like flops?  Absolutely not.

No memories come with resets.  Not DDR SDRAMs, not SRAMs, not BlockRAMs, not 
distributed CLB SelectRAMs, not TriMatrix Memory.

To clear the memory you either need to write every address or keep a 
separate bunch of registers as tags for each entry to label them as "not 
updated" in which case the value should be forced zero when read (at which 
time the flag is cleared).  Some people call these "dirty bits" to keep 
track of which entries provides clean data and which don't.

People who do fancy code can even have dirty bit registers to track a dirty 
bit memory array for those larger memory tasks.

The basic idea is:

  Clear:  Set all dirty bits.
  Read:  value <= Dirty[addr] ? 0 : yourMem[addr];  Dirty[addr] <= 0;


- John_H 

> To clear the memory you either need to write every address or keep a 
> separate bunch of registers as tags for each entry to label them as "not 
> updated" in which case the value should be forced zero when read (at which 
> time the flag is cleared).  Some people call these "dirty bits" to keep 
> track of which entries provides clean data and which don't.
> 
> People who do fancy code can even have dirty bit registers to track a dirty 
> bit memory array for those larger memory tasks.
> 
> The basic idea is:
> 
>   Clear:  Set all dirty bits.
>   Read:  value <= Dirty[addr] ? 0 : yourMem[addr];  Dirty[addr] <= 0;

Well, I would only clear the dirty bits on writes ...
Or if it's bram, you must force wren to 1 and write 0x00...00 at the same address you read to clear it.


	Sylvain

> To clear the memory you either need to write every address or keep a 
> separate bunch of registers as tags for each entry to label them as "not 
> updated" in which case the value should be forced zero when read (at which 
> time the flag is cleared).  Some people call these "dirty bits" to keep 
> track of which entries provides clean data and which don't.
> 
> People who do fancy code can even have dirty bit registers to track a dirty 
> bit memory array for those larger memory tasks.
> 
> The basic idea is:
> 
>   Clear:  Set all dirty bits.
>   Read:  value <= Dirty[addr] ? 0 : yourMem[addr];  Dirty[addr] <= 0;

Well, I would only clear the dirty bits on writes ...
Or if it's bram, you must force wren to 1 and write 0x00...00 at the same address you read to clear it.


	Sylvain

"Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote in 
message news:45F81941.2030603@youknowwhattodo.com...
>
>> To clear the memory you either need to write every address or keep a
>> separate bunch of registers as tags for each entry to label them as "not
>> updated" in which case the value should be forced zero when read (at 
>> which
>> time the flag is cleared).  Some people call these "dirty bits" to keep
>> track of which entries provides clean data and which don't.
>>
>> People who do fancy code can even have dirty bit registers to track a 
>> dirty
>> bit memory array for those larger memory tasks.
>>
>> The basic idea is:
>>
>>   Clear:  Set all dirty bits.
>>   Read:  value <= Dirty[addr] ? 0 : yourMem[addr];  Dirty[addr] <= 0;
>
> Well, I would only clear the dirty bits on writes ...
> Or if it's bram, you must force wren to 1 and write 0x00...00 at the same 
> address you read to clear it.
>
>
> Sylvain

Thanks for the clarification - my mistake.  You have things right, indeed. 

John is of course right. Memories have no global or parallel clear.
Such a clear would require an extra input to every data storage cell,
plus a wire interconnecting these inputs. Too expensive and too slow
in the highly competitive high-density RAM market.
Peter Alfke, Xilinx

On Mar 14, 8:33 am, "John_H" <newsgr...@johnhandwork.com> wrote:
> "Yrjola" <yrj...@op.pl> wrote in message
>
> news:et8ugq$uaq$1@node4.news.atman.pl...
>
> > Hi, I have set of registers implemented as internal RAM blocks (in Cyclone
> > FPGA). Is there any way to clear contents of this registers on demand
> > (just like clear signal in D flip-flops)?
>
> > For answers thanks in advance.
>
> Just like flops?  Absolutely not.
>
> No memories come with resets.  Not DDR SDRAMs, not SRAMs, not BlockRAMs, not
> distributed CLB SelectRAMs, not TriMatrix Memory.
>
> To clear the memory you either need to write every address or keep a
> separate bunch of registers as tags for each entry to label them as "not
> updated" in which case the value should be forced zero when read (at which
> time the flag is cleared).  Some people call these "dirty bits" to keep
> track of which entries provides clean data and which don't.
>
> People who do fancy code can even have dirty bit registers to track a dirty
> bit memory array for those larger memory tasks.
>
> The basic idea is:
>
>   Clear:  Set all dirty bits.
>   Read:  value <= Dirty[addr] ? 0 : yourMem[addr];  Dirty[addr] <= 0;
>
> - John_H

Peter Alfke wrote:

> John is of course right. Memories have no global or parallel clear.
> Such a clear would require an extra input to every data storage cell,
> plus a wire interconnecting these inputs. Too expensive and too slow
> in the highly competitive high-density RAM market.

I remember wondering some years ago (in the 8080 days) if SRAM
tended to power up to the same state.  It seemed that the screen
image on power up, before the software cleared the screen, tended
to be similar.  While a clear would be expensive, designing memory
cells, either SRAM or DRAM, to power up in a certain state might not
be as expensive.  I don't know that anyone has tried, though.

I also remember discussions about EPROMs that erase to
either 0 or 1, and which processors have opcode X'00' as NOOP.

-- glen

Glen, ten or fifteen years ago, it was possible to design latches =
memory cells in a slightly asymmetric way, so that they were
guaranteed to power-up in a specific state. That's what Xilinx did
originally with the many configuration memory cells. With smaller
geometries, this "trick" became unreliable, and Xilinx had to find a
different way to power up without massive contention. And we found :-)
Playing analog tricks becomes increasingly more cumbersome (and
unreliable) as we now are deep, deep in sub-micron territory.
Peter Alfke, Xilinx Applications

On Mar 15, 2:22 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Peter Alfke wrote:
> > John is of course right. Memories have no global or parallel clear.
> > Such a clear would require an extra input to every data storage cell,
> > plus a wire interconnecting these inputs. Too expensive and too slow
> > in the highly competitive high-density RAM market.
>
> I remember wondering some years ago (in the 8080 days) if SRAM
> tended to power up to the same state.  It seemed that the screen
> image on power up, before the software cleared the screen, tended
> to be similar.  While a clear would be expensive, designing memory
> cells, either SRAM or DRAM, to power up in a certain state might not
> be as expensive.  I don't know that anyone has tried, though.
>
> I also remember discussions about EPROMs that erase to
> either 0 or 1, and which processors have opcode X'00' as NOOP.
>
> -- glen

glen herrmannsfeldt wrote:
> Peter Alfke wrote:
> 
>> John is of course right. Memories have no global or parallel clear.
>> Such a clear would require an extra input to every data storage cell,
>> plus a wire interconnecting these inputs. Too expensive and too slow
>> in the highly competitive high-density RAM market.
> 
> I remember wondering some years ago (in the 8080 days) if SRAM
> tended to power up to the same state.  It seemed that the screen
> image on power up, before the software cleared the screen, tended
> to be similar.  While a clear would be expensive, designing memory
> cells, either SRAM or DRAM, to power up in a certain state might not
> be as expensive.  I don't know that anyone has tried, though.

DRAMs do not guarantee any specific power-up value but because they are built on 
femtofarad capacitors and somewhat leaky silicon, they should have a tendency to power-up 
mostly cleared. For SRAMs, I suspect results would indicate that they tend to power up 
with a specific device-unique pattern dictated by either the leakiest or strongest 
transistor in each bit and, given low-leakage transistors, it is not inconceivable that 
they may power-up biased towards their former power-on state.

Guaranteeing that an SRAM cell will always power-up cleared (without Peter's clear input 
and the extra cell transistors) would require making the SRAM cell leaky by design and 
that would be really bad for static power usage. While this "solution" does not cost any 
surface area, it would cost some power and decrease manufacturability: devices that would 
fail to power-up with all memories cleared but are in otherwise perfect working order 
would be out-of-spec and have to be either scrapped or sold as "dirty power-up" parts that 
consume something like 1W extra static power for no reason. 1W may be nothing to you but 
some people are working on low-power FPGA applications and would not dare touch such parts 
with a broomstick.

There aren't many applications where garbage memory content at power-up is a major issue 
and for the few cases where it may be so, there usually are a few simple work-arounds like 
having one reset for memories that need clearing and a second for everything else that 
gets stretched until the memory clearing processes are done.

> I also remember discussions about EPROMs that erase to
> either 0 or 1, and which processors have opcode X'00' as NOOP.

EPROMs work by trapping a charge in the matrix's isolated gate transistors. The UV 
exposure increases the cells' leakage current to clear the device while programming is 
done by "controlled failure" of the isolated gate to program 1s, this is why EPROMs have 
somewhat low reprogramming endurance.

glen herrmannsfeldt wrote:
> Peter Alfke wrote:
> 
>> John is of course right. Memories have no global or parallel clear.
>> Such a clear would require an extra input to every data storage cell,
>> plus a wire interconnecting these inputs. Too expensive and too slow
>> in the highly competitive high-density RAM market.
> 
> 
> I remember wondering some years ago (in the 8080 days) if SRAM
> tended to power up to the same state.  It seemed that the screen
> image on power up, before the software cleared the screen, tended
> to be similar.  While a clear would be expensive, designing memory
> cells, either SRAM or DRAM, to power up in a certain state might not
> be as expensive.  I don't know that anyone has tried, though.
> 
> I also remember discussions about EPROMs that erase to
> either 0 or 1, and which processors have opcode X'00' as NOOP.
> 
> -- glen
> 

Xilinx BRAMs do initialize in a known state on FPGA configuration.  The 
memory can be set to specific contents, or will default to all zero.