FPGA with 5V and PLCC package

Herbert Kleebauer wrote:
(snip)

> These are not electrical engineering but computer science students.
> Their job will be to design software and not hardware systems. But
> in order to do a proper software design, you need to understand the 
> principles of the underlying hardware so you get a feeling what a
> few lines of HL code can mean for the hardware.

> I don't know if all the supporters of VHDL/Verilog/HandleC here have 
> done low level logic development using a graphical representation and 
> just don't recognize how important that is to become a good designer
> at VHDL level or if they have never done this and still think they
> are good developers because the VHDL compiler is good enough and
> therefore they don't need to know anything about lower levels.

To me the question isn't graphical vs. textual, it is how well
one understands the underlying logic.

> Again the city map is a good example: If you want to drive from
> A to B, you call a taxi, the driver enters the target into the
> navigation system and this system mostly does a much better job
> you could do with the city map on your lap. So this is the best
> you can do if you know nothing about the city. But if you know 
> the layout of the city and you know that there is a river with
> only two bridges where you have to wait a long time because of
> the high traffic and you also know that there is a small bridge
> which could only be passed by foot, then you could do a much
> better job by driving to the small bridge, cross the river by foot
> and use an other taxi on the other side.

I agree with this one.  Though a good navigation system might
know about the bridge.  Some city bus systems have a computer
which will do route calculations.  That might include walking
across a bridge, otherwise it is up to the user to do that
before calling the taxi.

> The same is true for software: if you know how the hardware
> works you maybe can choose a different approach to solve the
> problem which is much more appropriate for the hardware. The
> compiler can do local optimizations extremely good, but the
> best global strategy has to be chosen by the programmer.
> And I think the same is true for hardware design. Just writing
> down VHDL statements without understanding the consequences
> for the generated hardware is not the way to go.

I completely agree with this statement.  One thing one must
learn, either with VHDL or graphical entry is the cost for each
logic block.  Just as in C programming, the tools don't help
much, one just has to learn it.

> The purpose of Universities is not to teach the students the
> use of tools but to teach them how to recognize, analyze and
> solve problems. The tools you use to solve the problems change
> rapidly but the ability to understand the source of a problem
> and analyze it from all angeles without using blinders is an
> essential requirement for the whole life.

I 100% agree here.  (Though I know a lot of people don't.)

> And as I said in the original posting, replacing the schematic
> entry by VHDL/Verilg isn't an alternative. All I wanted to know
> is, if somebody already was able to run the old Vielogic (DOS)
> on an actual OS (using a virtual machine). Or, whether there
> exists new FPGA's with a development system which is as easy
> to use as Viewlogic/DOS _AND_ where the chips are available
> in a package which could be soldered with a normal soldering
> iron on a self made non-multilayer PCP. I think there are
> both things available, but I didn't find the _AND_ combination.

In different discussions I have suggested that people should
remember the days of wiring up TTL gates on breadboards.
Using lower level HDL constructions is closer to that than
some higher level ones.  I don't know about VHDL, but you
can do verilog at the gate level.  That is, in addition
to behavioral and structural there is a level with references
to gate level primitives.

(snip)

> Sorry, but it really doesn't matter whether the AND gate is implemented
> as AND gate, by multiplexers or as a look-up table. They have learned
> that this all is equivalent and that the order of complexity is the
> same. But they must learn that there is big difference in the complexity
> for the ALU operation "add" and "div" and they don't see this in 
> the VHDL source code.

Thinks may have changed, last I knew the synthesis tools wouldn't
synthesize divide, at least not divide by a variable.  Maybe it is
just how much I hate using schematic entry tools.  If you draw
the design on paper using a gate template, maybe using 7400 series
logic blocks, and then write the corresponding HDL I don't think you
are missing out on anything.  I can probably do it with a minimal
hand drawn schematic, as I can solve algebraic equations without
doing all the intermediate steps, but it does still help to
write some down on paper.

-- glen

cs_posting@hotmail.com wrote:

> On Mar 22, 5:34 am, Herbert Kleebauer <k...@unibwm.de> wrote:

(snip)

>>I don't know if all the supporters of VHDL/Verilog/HandleC here have
>>done low level logic development using a graphical representation and
>>just don't recognize how important that is to become a good designer
>>at VHDL level.

> The problem I see is that you are making the assumption that
> _graphical representation_ is the only appropriate way to do low level
> design.  I'd argue it generally isn't.

I have to argue somewhere in between.  The designer should have some
idea about what is going on in the hardware.  For FPGA it isn't quite
as easy to see, so imagine a standard cell design instead.  For standard
cell the actual complexity is closer to that seen by the designer.

It does help to imagine it in terms of gates, just as a C programmer
can imagine his code in terms of machine instructions.  Though with
modern RISC machines you might be as far from what one can imagine
as FPGAs are from gates.  One should be able to choose a design
based on complexity or speed.  (Often speed is more important
than size, and that isn't so obvious if you can't imagine the
gate level.)

> More suitable low level design notations are things like minimum-sum-
> of-products equations, and the Karnough maps that one might use to
> create those by hand.  Sum of products is directly implementable in
> hardware - you could indeed have them draw some representative
> examples as gates.  But it's a much better notation system when you
> find it necessary to take the black boxes apart and look at their
> functionality.

One has to look at the problem at different levels.  One is the
gate level, another would have been the MSI level in TTL days,
adders, counters, multiplexers, decoders.  One doesn't need the
exact details (though I do still like to see the designs in the
TTL data book), but just to know how complex each one is or isn't.

(snip)

> A key reality that you are refusing to acknowledge is that you will
> not receive an actual "map to the city" of anything but a first-
> generation FPGA.  That kind of detail is proprietary.  What you get on
> the data sheet is a programming model, with a lot of things already
> hidden from you.  Using an FPGA to implement something that you've
> designed at the gate level is not a bad idea, but you must come to
> terms with the fact that your gate level design is only theoretical -
> even if you draw it in schematic entry, the tools is going to refactor
> it using its knowledge of the proprietary details of the hardware.

That is true, but as I said one can imagine it for standard cell.
One might even be able to run the synthesis and P&R for a standard
cell design to see how big or small things actually are.

(snip)

>>The same is true for software: if you know how the hardware
>>works you maybe can choose a different approach to solve the
>>problem which is much more appropriate for the hardware.

This is still very true for today's software.  Maybe even
more, as many of the old rules don't apply anymore.  With
overlapped execution it isn't easy to predict the timing for
even simple software projects.
(snip)

>>The purpose of Universities is not to teach the students the
>>use of tools but to teach them how to recognize, analyze and
>>solve problems. The tools you use to solve the problems change
>>rapidly but the ability to understand the source of a problem
>>and analyze it from all angeles without using blinders is an
>>essential requirement for the whole life.

> And ever since we stopped designing chips on single pieces of paper,
> the number one skill for a solving problems has been developing a
> healthy relationship with the _concept of abstraction_.

>>Sorry, but it really doesn't matter whether the AND gate is implemented
>>as AND gate, by multiplexers or as a look-up table. They have learned
>>that this all is equivalent and that the order of complexity is the
>>same. But they must learn that there is big difference in the complexity
>>for the ALU operation "add" and "div" and they don't see this in
>>the VHDL source code.

But the order of complexity really isn't the same.  A four input
exclusive or gate is much more complicated than a four input nand
gate made out of transistors, but not made out of LUTs.

> They most certainly will see this in the VHDL source code if you have
> require them to code up the ALU functionality from sufficiently small
> building blocks!
(snip)

> The moral?  Pick your  battles.  Your course project doesn't have
> anything that can't easily be implemented as gates and registers, so
> let your students implement in a gates and registers programming
> model.  But recognize that just because a language will let you
> utilize fancy functions like a hardware multiplier does not mean that
> you have to choose to do so, or let your students do so.

One should pick the appropriate blocks, either as schematic
capture or HDL.  Most schematic capture systems include a
library of logic blocks, probably similar to those available
in HDL.  Actually, more than the synthesis tools will generate
directly!

-- glen

Herbert Kleebauer wrote:
> Sorry, but it really doesn't matter whether the AND gate is implemented
> as AND gate, by multiplexers or as a look-up table. They have learned
> that this all is equivalent and that the order of complexity is the
> same. But they must learn that there is big difference in the complexity
> for the ALU operation "add" and "div" and they don't see this in 
> the VHDL source code.

In VHDL, you are correct, but in Boolean Eqn entry [CUPL], you have to 
manually 'build' the adder, so they are VERY much aware of the cost.
You can also see the ALU resource any time you glance at the
report file.
You can even discuss the trade-offs in adders, with speed/width,
if you want to, simply by letting the tools remove nodes, or not.
[try doing that in the SCH pathway ?]

-jg

msg wrote:
> Herbert Kleebauer wrote:
 
> > 2. Was somebody able to run Viewlogic (DOS version) in a virtual
> >    PC emulation.  The  problem is, the virtual PC must provide
> >    the proper graphics mode, mouse type and support a physical
> >    dongle on the virtual parallel port.
 
> Also, it would be an interesting experiment to try running
> the software on a VMWare MSDOS VM (a no-cost experiment); please
> report the results!

Downloaded Microsoft Virtual PC 2007 and installed it on a 3.4 GHz P4
with Windows XP. Workview runs on a DOS 6.22 installation on the virtual 
PC (the parallel port dongle works) but needs an extra mouse on the serial 
port (the Windows USB mouse is not recognized by Workview). But it's not
usable because it is extremely slow (slower than on a 486), especially the
mouse movements.

Herbert Kleebauer wrote:

> 1. I have tried to find an actual FPGA with a package which can
>    be soldered with a non professional equipment, something like
>    a PLCC84 where you can get cheap sockets which can be used on

Does anybody know whether there is a company which sells Spartan3
chips (or any other FPGA type) already soldered to an adaptor board
like:

http://www.rsonline.de/cgi-bin/bv/rswww/searchBrowseAction.do?N=0&Ntk=I18NAll&Ntt=295-4331

Preferable with the GND an VCC pins already connected and capacitors
on the adapter.

"Herbert Kleebauer" <klee@unibwm.de> wrote in message 
news:460B70A6.4096E0CA@unibwm.de...
> Herbert Kleebauer wrote:
>
>> 1. I have tried to find an actual FPGA with a package which can
>>    be soldered with a non professional equipment, something like
>>    a PLCC84 where you can get cheap sockets which can be used on
>
> Does anybody know whether there is a company which sells Spartan3
> chips (or any other FPGA type) already soldered to an adaptor board
> like:
>
> http://www.rsonline.de/cgi-bin/bv/rswww/searchBrowseAction.do?N=0&Ntk=I18NAll&Ntt=295-4331
>
> Preferable with the GND an VCC pins already connected and capacitors
> on the adapter.
>
Hi Herbert,
Apart from the ones John mentioned?
http://www.enterpoint.co.uk/component_replacements/craignell.html

Also, this might help.

http://www.fpga-faq.com/FPGA_Boards.shtml

I wonder, given that you're in the computer science faculty, have you spoken 
to the guys in EE to ask for their help? Just a thought...

Good luck, Syms. 

Symon wrote:
> "Herbert Kleebauer" <klee@unibwm.de> wrote in message

> > Does anybody know whether there is a company which sells Spartan3
> > chips (or any other FPGA type) already soldered to an adaptor board
> > like:
> >
> > http://www.rsonline.de/cgi-bin/bv/rswww/searchBrowseAction.do?N=0&Ntk=I18NAll&Ntt=295-4331
> >
> > Preferable with the GND an VCC pins already connected and capacitors
> > on the adapter.
> >
> Hi Herbert,
> Apart from the ones John mentioned?
> http://www.enterpoint.co.uk/component_replacements/craignell.html
> 
> Also, this might help.
> 
> http://www.fpga-faq.com/FPGA_Boards.shtml

Yes I know, there are many development boards, but we don't want a
board but the chip. As there is a big difference whether you make 
a design at gate level using a schematic entry or use high level 
VHDL code, there also is a big difference whether you buy a CPU and 
built a computer system or you buy a ready to use motherboard to built 
a computer system. The same is true for FPGA's and ready to use FPGA 
development boards. You have to go at least once to the low level to 
understand the problems, then you can do it at a higher level.

Herbert Kleebauer wrote:

> Symon wrote:
> 
>>"Herbert Kleebauer" <klee@unibwm.de> wrote in message
> 
> 
>>>Does anybody know whether there is a company which sells Spartan3
>>>chips (or any other FPGA type) already soldered to an adaptor board
>>>like:
>>>
>>>http://www.rsonline.de/cgi-bin/bv/rswww/searchBrowseAction.do?N=0&Ntk=I18NAll&Ntt=295-4331
>>>
>>>Preferable with the GND an VCC pins already connected and capacitors
>>>on the adapter.
>>>
>>
>>Hi Herbert,
>>Apart from the ones John mentioned?
>>http://www.enterpoint.co.uk/component_replacements/craignell.html
>>
>>Also, this might help.
>>
>>http://www.fpga-faq.com/FPGA_Boards.shtml
> 
> 
> Yes I know, there are many development boards, but we don't want a
> board but the chip. As there is a big difference whether you make 
> a design at gate level using a schematic entry or use high level 
> VHDL code, there also is a big difference whether you buy a CPU and 
> built a computer system or you buy a ready to use motherboard to built 
> a computer system. The same is true for FPGA's and ready to use FPGA 
> development boards. You have to go at least once to the low level to 
> understand the problems, then you can do it at a higher level.

Yes, I can follow that, but then why not use a PLCC CPLD, for the hardware ?
That is further to the low level, than a FPGA ?

-jg

Herbert Kleebauer wrote:

>We use in a laboratory course still XILINX XC3000 FPGAs with
>Viewlogic's Workview design entry (DOS version) and XILINX
>XACT (also DOS). The problem is that we have to replace the 
>old PC's and that Viewlogic only supports a few graphics modes 
>and it is unlikely that it will run on new PC's. The last
>version of XILINX ISE software which supports XC3000 FPGA's
>isn't an alternative (and I'm not sure whether it will
>run on W2k/XP) because the system must be extremely easy to
>use so the students are able to design and implement a simple
>CPU in about 10 hours (including the time to learn how to use
>the schematic entry and simulation tool).
>
>Some questions:
>
>1. I have tried to find an actual FPGA with a package which can
>   be soldered with a non professional equipment, something like
>   a PLCC84 where you can get cheap sockets which can be used on
>
You can use Xilinx Spartan chips such as XCS10-xPC84 (x is the speed grade).
I don't remember how big the array goes in the PC84 package.  With a 
little more
soldering skill, there are flat pack Spartan chips, such as 144-pin.

You need to use Xilinx's ise 5.2 or earlier software to generate configs 
for these
older chips.  Despite Xilinx pulling all references to them off their 
web site,
the 5 V Spartans are still available.  They are a little harder to get 
in small quantity,
but if you need 50 or something, it would be no problem.

>   self made PCBs and if possible with a VCC of 5 V to easy interface
>   with external TTL logic. XILINX and ACTEL only offers packages with
>  
>
Jon

Herbert Kleebauer wrote:

>The problem is not the money, but the time of the students.
>The system must be very easy to use so the students can built
>the simple CPU at gate level in 10 hours including the time to 
>learn the tools.
>
This is a fantasy!  You could probably design a 2-bit adder at the gate
level in 10 hours, starting from not knowing the package.  There is no
way a student could design a CPU at the gate level, unless it was maybe
a Turing machine (one-bit CPU), in 10 hours.  Even if they were fluent in
VHDL, every toolkit has its own dialect of what is accepted and what is
not.  Then, you have to learn the simulator, how to write test benches,
debug the board, the FPGA soldering, testing the FPGA config ON the
target board.....

I run Xilinx ise 5.1 and 5.2 on Windows 2000.  I'm still working in the
5 V world for a little while longer.

Jon