FPGA with 5V and PLCC package

Herbert Kleebauer wrote:

>msg wrote:
>  
>
>>Herbert Kleebauer wrote:
>>    
>>
> 
>  
>
>>>2. Was somebody able to run Viewlogic (DOS version) in a virtual
>>>   PC emulation.  The  problem is, the virtual PC must provide
>>>   the proper graphics mode, mouse type and support a physical
>>>   dongle on the virtual parallel port.
>>>      
>>>
> 
>  
>
>>Also, it would be an interesting experiment to try running
>>the software on a VMWare MSDOS VM (a no-cost experiment); please
>>report the results!
>>    
>>
>
>  
>
I run Xilinx ise 5.2 on Windows 2000 under VMware, using Linux as the host
OS.  Win 2K is MUCH more reliable under VMware than on real hardware.
It stays up for months at a time.  I program EPROMS and download to CPLDs
through the JTAG on the parallel Cable III pod.

Jon

cs_posting@hotmail.com wrote:

>But the fact of the matter is that there is hidden technology at all
>levels of the system.  As has been pointed out, the tools don't
>implement the actual gates you've drawn, they implement a logical
>equivelent.  And there's also sorts of hidden semi-proprietary stuff
>on the FPGA die.  You may find this easier to ignore with an older
>part, but it's still true.  Unless you go back to very raw TTL type
>chips (or maybe even earlier), what your students will be designing
>with is a black box abstraction that _does not really match_ its
>logical symbol representation except in explicit ways the data sheet
>says it does.
>
>  
>
The abstraction of the logic doesn't matter in the sense of a truth 
table (as long
as it is complete).  The result will match the truth table for sure. 
 But, the actual
logic pathways will not bear any resemblence to the schematics, and so 
the timing
will be radically different than what is drawn.  Of course, with good 
logic design,
it will still meet the design spec, but with crummy design planning, it 
sure won't.

Jon

Jon Elson wrote:
> 
> 
> Herbert Kleebauer wrote:
> 
>> The problem is not the money, but the time of the students.
>> The system must be very easy to use so the students can built
>> the simple CPU at gate level in 10 hours including the time to learn 
>> the tools.
>>
> This is a fantasy!  You could probably design a 2-bit adder at the gate
> level in 10 hours, starting from not knowing the package.  There is no
> way a student could design a CPU at the gate level, unless it was maybe
> a Turing machine (one-bit CPU), in 10 hours.  Even if they were fluent in
> VHDL, every toolkit has its own dialect of what is accepted and what is
> not.  Then, you have to learn the simulator, how to write test benches,
> debug the board, the FPGA soldering, testing the FPGA config ON the
> target board.....

  I think Herbert was using the time, to illustrate the need for 
schematic flow, and built might not have meant physically assemble
a PCB, but probably includes bitstream and prom generate.

  You are both right - Herbert has a very short time or this section of 
the course, and yes, full VHDL Xilinx tool flows, will have too long a 
learning curve.

  His ideal is to continue to run the old Viewlogic system, and I
think some posts offered some hope.

  Failing that, I've suggested a Boolean Eqn entry scheme, that does
have a shorter learning curve, and is quick to run - and that is
close enough to the gate-level to see the AND.OR.Registers

  I have one ToolChain here, on a Flash drive, in under 10MB.

-jg

Jon Elson wrote:> 
> Herbert Kleebauer wrote:
> 
> >The problem is not the money, but the time of the students.
> >The system must be very easy to use so the students can built
> >the simple CPU at gate level in 10 hours including the time to
> >learn the tools.
> >
> This is a fantasy!  You could probably design a 2-bit adder at the gate
> level in 10 hours, starting from not knowing the package.  There is no
> way a student could design a CPU at the gate level, unless it was maybe
> a Turing machine (one-bit CPU), in 10 hours.  Even if they were fluent in
> VHDL, every toolkit has its own dialect of what is accepted and what is
> not.  Then, you have to learn the simulator, how to write test benches,

Then this fantasy has become true since many years. This is a 12 week lecture
about computer organization an we have 45 min time every week for exercises.
We have combined this time to 3 x 3 hours to reduce overhead. The first
3 hours are mostly needed to explain and discuss the processor architecture
and to get familiar with the VIELOGIC system. So there only 6 hours left
to implement and test the CPU (some groups need a few additional hours,
but they are willing to spend this extra time because most of them are
really interested). They don't have to start from zero, the design is 
given at block level, but all the gates and flip-flops they have to
insert and wire themselves. And this is not a 1-bit CPU, but a 16 bit
processor (which can address 64 kbyte external memory) with external 
interrupt support and built-in IO (8 input and 8 output lines).

> debug the board, the FPGA soldering, testing the FPGA config ON the
> target board.....

The board already exists, all they have to do is to generate the 
bitstream to download. (I have posted a link to the description
of the course in the OP, the documentation the students get is:
ftp://137.193.64.130/pub/mproz/mproz_ub.pdf ).

> >
> >1. I have tried to find an actual FPGA with a package which can
> >   be soldered with a non professional equipment, something like
> >   a PLCC84 where you can get cheap sockets which can be used on
> >
> You can use Xilinx Spartan chips such as XCS10-xPC84 (x is the speed grade).
> I don't remember how big the array goes in the PC84 package.  With a

Yes, but the actual software doesn't support this chips anymore. We also
could go back to the last version which supports XC3000 so we could use
the current hardware. But I'm not even sure whether this version runs
in XP. If we have to make a cut and drop the old system, then we don't
want to replace it with something which also isn't supported anymore.

I would like to use an actual system which we could use for the next
8-10 years without modification (like we did with VIELOGIC/XC3000).
But maybe we have to drop the hardware completely and finish the 
course after the simulation. But it was always a big motivation for
the students to finally seE the processor running on a simple PCP
board with nothing than an FPGA, EPROM, SRAM and a few LED's.

Hebert,

   As a recent student myself (been doing FPGA design for 2 years now)
I've gotta say....  HDL.

   Actual FPGA design flow, in the real world, is

Preliminary Design - Block Diagrams
Detailed Desgin - HDL
Verification - HDL

In terms of getting an idea of how many flops and gates (you said they
should be able
to get an idea for the scale of the design) all you have to do is not
allow
them to use high level constructs.

A <= B AND C;

1 line of code = 1 gate.....

That would make them go through the labor of explicitly understanding
every single gate, but yet expose them to something they might
actually
use in their career - something they can build off of in future
classes or a future
job.

I took a intro digital design class.... we learned carnot maps and the
rest of it...
next semester, the professor for the advanced class tells us "You'll
never actually
use any of that - the synthesizer will do all that for you... and
given the architecture
of the logic device you're using the fully reduced function is not
always the most
efficient, because that 4 input LUT is there whether you use it or
not"  Sure enough
take a quick when the last time I used a carnot map was... I wouldnt
remember how.
The one lesson learned from that first class "Logic is reducable" the
reality learned in the
second class "your design tools will do that for you".  There was a
very good reason why the
first class did NOT have a lab associated with it... cause making us
hook up discrete AND and
OR gates in DIP packages would have zero bearing on our careers.  The
second class
had a GREAT lab associated with it that used a Virtex2.

At any rate... just the opinion of a recent student.  If you can't
teach everything you need to
in HDL, then you need to go back and learn HDL a littler better.





On Mar 21, 6:22 am, Herbert Kleebauer <k...@unibwm.de> wrote:
> Symon wrote:
> > If it's OK, I have an observation. I wonder why these students are being
> > taught design methods on design tools and FPGA parts that most folks on this
> > newsgroup haven't used for a long time. The schematic vs. HDL wars have long
> > since died down because modern FPGA designs are generally 'better'
> > implemented using HDLs.
>
> This is an exercise to a lecture about computer organization. The student
> have just learned how to make a truth table, minimize logic functions and
> design simple state machines. In this exercise they should use this
> knowledge to implement a little bit more complex design. And what
> can be more interesting than designing your own CPU. Therefore VHDL
> isn't any alternative, they are only allowed to use D-FF's and simple
> gates like AND,OR,NAND,NOR. We could stop the course after simulating
> the design, but it is much more motivating when at the end your CPU
> is running in hardware. But this hardware has to be a simple hardware
> (not one of this complex multilayer FPGA prototyping boards) so they
> see that there is no hidden technology and they even could make the
> same board at home with an cheap soldering iron.
>
> > p.s. I HATE Viewlogic. I wasted a day on a legacy design a while back
> > because a wire had the wrong shaped dot on it. The worst part was the bloody
> > software guy spotted the mistake!
>
> Maybe you didn't use the DOS version. I suppose this software
> was made by hardware engineers to support there work. An it
> was so good that other people also wanted it. But with the
> success of the tool the company hired software engineers and
> these people can destroy any perfect usable SW in nearly no
> time. I installed the Windows version of WorkView when it was
> available, but after testing immediately deleted it. The
> same happened a few years before with the Daisy CAD system.