shift register with distributed ram

John McCaskill wrote:


> The SLR16s have two outputs that can be used for serial to parallel
> shifters, the Q15 for cascading, and the selectable output.  I finally
> found the article that describes how to use an SRL plus a FF to build
> a 6 bit per slice serial to parallel shifter. It is by Kris Chaplin,
> not Ken Chapman like I had been thinking.
> 

This works nicely as long as you don't need speed.  The direct outputs 
(ie not through the slice register) from the SRL16 are quite slow.  Even 
just routing the SRL output directly to a flip-flop in another slice 
yields a huge minimum clock hit.

 "Slow" (and "fast") are very nebulous statements. Losing a few
nanoseconds in an interconnect is o.k. when the clock runs at 100 MHz,
or even a bit faster...
Peter Alfke

On Mar 30, 2:46 pm, Ray Andraka <r...@andraka.com> wrote:
> John McCaskill wrote:
> > The SLR16s have two outputs that can be used for serial to parallel
> > shifters, the Q15 for cascading, and the selectable output.  I finally
> > found the article that describes how to use an SRL plus a FF to build
> > a 6 bit per slice serial to parallel shifter. It is by Kris Chaplin,
> > not Ken Chapman like I had been thinking.
>
> This works nicely as long as you don't need speed.  The direct outputs
> (ie not through the slice register) from the SRL16 are quite slow.  Even
> just routing the SRL output directly to a flip-flop in another slice
> yields a huge minimum clock hit.

Peter Alfke wrote:

>  "Slow" (and "fast") are very nebulous statements. Losing a few
> nanoseconds in an interconnect is o.k. when the clock runs at 100 MHz,
> or even a bit faster...
> Peter Alfke

And a killer when the clock runs at 250 MHz.  100MHz is slow in modern 
FPGAs...slow compared to what the FPGA is capable of with careful design.