Hi, When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would like to know which patents filed by Xilinx to disclose the contents of Slice L. Slice M is too complex for me to fully understand at the moment and just knowledge of Slice L is good enough for me to start with Virtex-5 as basic knowledge for it. Thank you. Weng
What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
Started by ●March 27, 2007
Reply by ●March 27, 20072007-03-27
Is page 158 of the Virtex-5 User Guide http://direct.xilinx.com/bvdocs/userguides/ug190.pdf just too darned simple for you? Are you trying to understand the operation of the part from the detailed silicon level tricks that may or may not be applicable for this part of the device? I tried looking at a DDR IOB cell patent once and found it to be interestingly disconnected from my RTL and chip level design experience. If you are into physical level design of CMOS chips on advanced processes you have a chance of understanding how things come together. If all you want to know is how that chip will work for you, use the User's Guide! I don't have to know about the metal casting used for the alternator in my car to understand how the alternator works. You don't need patents to understand the SLICE_L. - John_H "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1175036266.831589.180920@b75g2000hsg.googlegroups.com...> Hi, > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > like to know which patents filed by Xilinx to disclose the contents of > Slice L. > > Slice M is too complex for me to fully understand at the moment and > just knowledge of Slice L is good enough for me to start with Virtex-5 > as basic knowledge for it. > > Thank you. > > Weng
Reply by ●March 27, 20072007-03-27
On Mar 27, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote:> Is page 158 of the Virtex-5 User Guide > > http://direct.xilinx.com/bvdocs/userguides/ug190.pdf > > just too darned simple for you? Are you trying to understand the operation > of the part from the detailed silicon level tricks that may or may not be > applicable for this part of the device? I tried looking at a DDR IOB cell > patent once and found it to be interestingly disconnected from my RTL and > chip level design experience. If you are into physical level design of CMOS > chips on advanced processes you have a chance of understanding how things > come together. If all you want to know is how that chip will work for you, > use the User's Guide! > > I don't have to know about the metal casting used for the alternator in my > car to understand how the alternator works. You don't need patents to > understand the SLICE_L. > > - John_H > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > news:1175036266.831589.180920@b75g2000hsg.googlegroups.com... > > > > > Hi, > > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > > like to know which patents filed by Xilinx to disclose the contents of > > Slice L. > > > Slice M is too complex for me to fully understand at the moment and > > just knowledge of Slice L is good enough for me to start with Virtex-5 > > as basic knowledge for it. > > > Thank you. > > > Weng- Hide quoted text - > > - Show quoted text -Hi John, Yes, I am interested in ASIC design of Slice L and want someone's help to locate the patent filed by Xilinx that contains the contents of Slice L. I am not interested in slice M that is too complex to me now. I have already printed the user manual you indicated and carefully read it. But it doesn't meet my curiority. Weng
Reply by ●March 27, 20072007-03-27
Weng, you seem to believe that there is a one-to-one corresponcence between the content of a patent and the Xilinx implementation. That is not necessarily so. If you want to learn what a certain company is interested in, then looking at patents is meaningful, (but you still suffer from the 2- to-4year delay in patent issuing.) If you want to design an ASIC, intimate knowledge of the FPGA may be more hindrance than help. The architecture and circuit trade-offs are completely different. Keep studying... Peter Alfke ========================== On Mar 27, 6:10 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote:> On Mar 27, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > > Is page 158 of the Virtex-5 User Guide > > > http://direct.xilinx.com/bvdocs/userguides/ug190.pdf > > > just too darned simple for you? Are you trying to understand the operation > > of the part from the detailed silicon level tricks that may or may not be > > applicable for this part of the device? I tried looking at a DDR IOB cell > > patent once and found it to be interestingly disconnected from my RTL and > > chip level design experience. If you are into physical level design of CMOS > > chips on advanced processes you have a chance of understanding how things > > come together. If all you want to know is how that chip will work for you, > > use the User's Guide! > > > I don't have to know about the metal casting used for the alternator in my > > car to understand how the alternator works. You don't need patents to > > understand the SLICE_L. > > > - John_H > > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > >news:1175036266.831589.180920@b75g2000hsg.googlegroups.com... > > > > Hi, > > > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > > > like to know which patents filed by Xilinx to disclose the contents of > > > Slice L. > > > > Slice M is too complex for me to fully understand at the moment and > > > just knowledge of Slice L is good enough for me to start with Virtex-5 > > > as basic knowledge for it. > > > > Thank you. > > > > Weng- Hide quoted text - > > > - Show quoted text - > > Hi John, > Yes, I am interested in ASIC design of Slice L and want someone's help > to locate the patent filed by Xilinx that contains the contents of > Slice L. I am not interested in slice M that is too complex to me now. > > I have already printed the user manual you indicated and carefully > read it. But it doesn't meet my curiority. > > Weng
Reply by ●March 28, 20072007-03-28
Hi, Due to recent changes, the 2-to-4 year delay has been reduced somewhat. If you go to http://www.uspto.gov/patft/, you can now view published applications. I'm not sure how soon after filing that an application is made available to the public, but based on random searches of the patents of my colleagues it seems like it is in the neighborhood of 1 year. I agree with Peter -- rarely will you see what exactly was implemented in the chip in a patent; it is usually some combination of a bunch of patents mixed with good engineering and a dash of trade secrets. And it can be hard to tell what a patent was really about by the time it gets turned into legalize... - Paul
Reply by ●March 28, 20072007-03-28
On Mar 27, 7:15 pm, "Peter Alfke" <a...@sbcglobal.net> wrote:> Weng, you seem to believe that there is a one-to-one corresponcence > between the content of a patent and the Xilinx implementation. > That is not necessarily so. > If you want to learn what a certain company is interested in, then > looking at patents is meaningful, (but you still suffer from the 2- > to-4year delay in patent issuing.) > If you want to design an ASIC, intimate knowledge of the FPGA may be > more hindrance than help. The architecture and circuit trade-offs are > completely different. > Keep studying... > Peter Alfke > ========================== > > On Mar 27, 6:10 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > On Mar 27, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > Is page 158 of the Virtex-5 User Guide > > > > http://direct.xilinx.com/bvdocs/userguides/ug190.pdf > > > > just too darned simple for you? Are you trying to understand the operation > > > of the part from the detailed silicon level tricks that may or may not be > > > applicable for this part of the device? I tried looking at a DDR IOB cell > > > patent once and found it to be interestingly disconnected from my RTL and > > > chip level design experience. If you are into physical level design of CMOS > > > chips on advanced processes you have a chance of understanding how things > > > come together. If all you want to know is how that chip will work for you, > > > use the User's Guide! > > > > I don't have to know about the metal casting used for the alternator in my > > > car to understand how the alternator works. You don't need patents to > > > understand the SLICE_L. > > > > - John_H > > > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > > >news:1175036266.831589.180920@b75g2000hsg.googlegroups.com... > > > > > Hi, > > > > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > > > > like to know which patents filed by Xilinx to disclose the contents of > > > > Slice L. > > > > > Slice M is too complex for me to fully understand at the moment and > > > > just knowledge of Slice L is good enough for me to start with Virtex-5 > > > > as basic knowledge for it. > > > > > Thank you. > > > > > Weng- Hide quoted text - > > > > - Show quoted text - > > > Hi John, > > Yes, I am interested in ASIC design of Slice L and want someone's help > > to locate the patent filed by Xilinx that contains the contents of > > Slice L. I am not interested in slice M that is too complex to me now. > > > I have already printed the user manual you indicated and carefully > > read it. But it doesn't meet my curiority. > > > Weng- Hide quoted text - > > - Show quoted text -Hi Peter, Thank you for your advice. I like reading and learning. Your paper about asynchronous FIFO cooperated with another engineer is the best article I have read in my life. Weng
Reply by ●March 30, 20072007-03-30
On Mar 27, 8:44 pm, "Paul Leventis" <paul.leven...@gmail.com> wrote:> Hi, > > Due to recent changes, the 2-to-4 year delay has been reduced > somewhat. If you go tohttp://www.uspto.gov/patft/, you can now view > published applications. I'm not sure how soon after filing that an > application is made available to the public, but based on random > searches of the patents of my colleagues it seems like it is in the > neighborhood of 1 year. > > I agree with Peter -- rarely will you see what exactly was implemented > in the chip in a patent; it is usually some combination of a bunch of > patents mixed with good engineering and a dash of trade secrets. And > it can be hard to tell what a patent was really about by the time it > gets turned into legalize... > > - PaulHi Paul, Can you help identify where I can find the patent application: U.S. Appl No. 11/151/796, filed Jun. 14, 2005. It is said that a patent application will be published after 180 days since its file date. But from U.S. Patent Office, I couldn't find it. Why? Or any other technology to find it? Or it may be delayed longer than 180 days? Weng
Reply by ●March 31, 20072007-03-31
Weng, I am glad you liked the paper. Here it is: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf Both Cliff Cummins and I are deeply involved in the peculiarities of asynchr. FIFOs. When we agreed to co-author this paper, Cliff was very suspicious that my solution would not work properly, so I had to work very hard to (almost) convince him. That definitely improved the paper, which was then voted "best paper of the conference"(Synopsys User Group, 2002) Nice memories... Thanks Peter Alfke On Mar 27, 10:03 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote:> On Mar 27, 7:15 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > > > > > Weng, you seem to believe that there is a one-to-one corresponcence > > between the content of a patent and the Xilinx implementation. > > That is not necessarily so. > > If you want to learn what a certain company is interested in, then > > looking at patents is meaningful, (but you still suffer from the 2- > > to-4year delay in patent issuing.) > > If you want to design an ASIC, intimate knowledge of the FPGA may be > > more hindrance than help. The architecture and circuit trade-offs are > > completely different. > > Keep studying... > > Peter Alfke > > ========================== > > > On Mar 27, 6:10 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > On Mar 27, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > > Is page 158 of the Virtex-5 User Guide > > > > > http://direct.xilinx.com/bvdocs/userguides/ug190.pdf > > > > > just too darned simple for you? Are you trying to understand the operation > > > > of the part from the detailed silicon level tricks that may or may not be > > > > applicable for this part of the device? I tried looking at a DDR IOB cell > > > > patent once and found it to be interestingly disconnected from my RTL and > > > > chip level design experience. If you are into physical level design of CMOS > > > > chips on advanced processes you have a chance of understanding how things > > > > come together. If all you want to know is how that chip will work for you, > > > > use the User's Guide! > > > > > I don't have to know about the metal casting used for the alternator in my > > > > car to understand how the alternator works. You don't need patents to > > > > understand the SLICE_L. > > > > > - John_H > > > > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > > > >news:1175036266.831589.180920@b75g2000hsg.googlegroups.com... > > > > > > Hi, > > > > > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > > > > > like to know which patents filed by Xilinx to disclose the contents of > > > > > Slice L. > > > > > > Slice M is too complex for me to fully understand at the moment and > > > > > just knowledge of Slice L is good enough for me to start with Virtex-5 > > > > > as basic knowledge for it. > > > > > > Thank you. > > > > > > Weng- Hide quoted text - > > > > > - Show quoted text - > > > > Hi John, > > > Yes, I am interested in ASIC design of Slice L and want someone's help > > > to locate the patent filed by Xilinx that contains the contents of > > > Slice L. I am not interested in slice M that is too complex to me now. > > > > I have already printed the user manual you indicated and carefully > > > read it. But it doesn't meet my curiority. > > > > Weng- Hide quoted text - > > > - Show quoted text - > > Hi Peter, > Thank you for your advice. > > I like reading and learning. Your paper about asynchronous FIFO > cooperated with another engineer is the best article I have read in my > life. > > Weng
Reply by ●April 1, 20072007-04-01
On Mar 30, 8:09 pm, "Peter Alfke" <a...@sbcglobal.net> wrote:> Weng, I am glad you liked the paper. Here it is:http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf > > Both Cliff Cummins and I are deeply involved in the peculiarities of > asynchr. FIFOs. When we agreed to co-author this paper, Cliff was very > suspicious that my solution would not work properly, so I had to work > very hard to (almost) convince him. That definitely improved the > paper, which was then voted "best paper of the conference"(Synopsys > User Group, 2002) > Nice memories... > Thanks > Peter Alfke > > On Mar 27, 10:03 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > On Mar 27, 7:15 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > > > > Weng, you seem to believe that there is a one-to-one corresponcence > > > between the content of a patent and the Xilinx implementation. > > > That is not necessarily so. > > > If you want to learn what a certain company is interested in, then > > > looking at patents is meaningful, (but you still suffer from the 2- > > > to-4year delay in patent issuing.) > > > If you want to design an ASIC, intimate knowledge of the FPGA may be > > > more hindrance than help. The architecture and circuit trade-offs are > > > completely different. > > > Keep studying... > > > Peter Alfke > > > ========================== > > > > On Mar 27, 6:10 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > On Mar 27, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > > > Is page 158 of the Virtex-5 User Guide > > > > > > http://direct.xilinx.com/bvdocs/userguides/ug190.pdf > > > > > > just too darned simple for you? Are you trying to understand the operation > > > > > of the part from the detailed silicon level tricks that may or may not be > > > > > applicable for this part of the device? I tried looking at a DDR IOB cell > > > > > patent once and found it to be interestingly disconnected from my RTL and > > > > > chip level design experience. If you are into physical level design of CMOS > > > > > chips on advanced processes you have a chance of understanding how things > > > > > come together. If all you want to know is how that chip will work for you, > > > > > use the User's Guide! > > > > > > I don't have to know about the metal casting used for the alternator in my > > > > > car to understand how the alternator works. You don't need patents to > > > > > understand the SLICE_L. > > > > > > - John_H > > > > > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > > > > >news:1175036266.831589.180920@b75g2000hsg.googlegroups.com... > > > > > > > Hi, > > > > > > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > > > > > > like to know which patents filed by Xilinx to disclose the contents of > > > > > > Slice L. > > > > > > > Slice M is too complex for me to fully understand at the moment and > > > > > > just knowledge of Slice L is good enough for me to start with Virtex-5 > > > > > > as basic knowledge for it. > > > > > > > Thank you. > > > > > > > Weng- Hide quoted text - > > > > > > - Show quoted text - > > > > > Hi John, > > > > Yes, I am interested in ASIC design of Slice L and want someone's help > > > > to locate the patent filed by Xilinx that contains the contents of > > > > Slice L. I am not interested in slice M that is too complex to me now. > > > > > I have already printed the user manual you indicated and carefully > > > > read it. But it doesn't meet my curiority. > > > > > Weng- Hide quoted text - > > > > - Show quoted text - > > > Hi Peter, > > Thank you for your advice. > > > I like reading and learning. Your paper about asynchronous FIFO > > cooperated with another engineer is the best article I have read in my > > life. > > > Weng- Hide quoted text - > > - Show quoted text -Hi Peter, Yes, I had printed the paper 5 years ago and read it very carefully and the paper teaches me how to understand and handle the asynchronous situation. The paper not only won the first prize of the conference, but also won my highest comment: it is the best paper I have read in my life !!! Thank you and Cliff Cummins for the excellent paper that really made contributions to the VHDL world. Weng
