Hi,
I build a IPIF master with Create/Import Peripheral.
I try the example write in the user_logic.vhd:
-- Here's an example procedure in your software application to
initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the source data address (local) to the ip2ip register
-- 3. write the destination address (remote) to the ip2bus
register
-- - note: this address will be put on the target bus address
line
-- 4. write 0x0004 to the length register
-- 5. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 6. write 0x0a to the go register, this will start the write
operation
My C:
#include "xparameters.h"
#include "xutil.h"
int main (void) {
volatile Xuint32* Data;
Data=3D(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR;
// contr=F4l register
Data=3D(Xuint32*)(0x00+0x00);
*(Data)=3D0x40;
// source address
Data=3D(Xuint32*)(0x00+0x04);
*(Data)=3DXPAR_TEST_0_BASEADDR;
//destination address
Data=3D(Xuint32*)(0x00+0x04);
*(Data)=3DXPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR;
// lengh register
Data=3D(Xuint32*)(0x00+0x04);
*(Data)=3D0x04;
// BE register
Data=3D(Xuint32*)(0x00+0x02);
*(Data)=3D0xFF;
// Go register
Data=3D(Xuint32*)(0x00+0x01);
*(Data)=3D0x0A;
return 0;
}
I put one data in my TEST block, but nothing happened.
I want to transfer the data from the TEST block to a BRAM with this
IPIF, but i don't understand
what address i need to put in my TEST block to access to my BRAM.
Can you help me ????
Thanks
PLB Master
Started by ●April 16, 2007
Reply by ●April 16, 20072007-04-16
"LilacSkin" <lpaulo07@iseb.fr> wrote in message news:1176715616.959521.180000@b75g2000hsg.googlegroups.com...> Hi,> I build a IPIF master with Create/Import Peripheral. > I try the example write in the user_logic.vhd:> volatile Xuint32* Data; > Data=(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR; > > // contr�l register > Data=(Xuint32*)(0x00+0x00); > *(Data)=0x40;You just overwrite your "Data" pointer. Unless XPAR_IPIF_MASTER_0_BASEADDR is 0, you won't be accessing your peripheral. Didn't you mean Data=(Xuint32*)(XPAR_IPIF_MASTER_0_BASEADDR+0x00); ...and so on? -Ben-
Reply by ●April 16, 20072007-04-16
On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote:> "LilacSkin" <lpaul...@iseb.fr> wrote in message > > news:1176715616.959521.180000@b75g2000hsg.googlegroups.com... > > > Hi, > > I build a IPIF master with Create/Import Peripheral. > > I try the example write in the user_logic.vhd: > > volatile Xuint32* Data; > > Data=3D(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR; > > > // contr=F4l register > > Data=3D(Xuint32*)(0x00+0x00); > > *(Data)=3D0x40; > > You just overwrite your "Data" pointer. Unless XPAR_IPIF_MASTER_0_BASEADDR > is 0, you won't be accessing your peripheral. > > Didn't you mean > > Data=3D(Xuint32*)(XPAR_IPIF_MASTER_0_BASEADDR+0x00); > > ...and so on? > > -Ben-No change, There is something i don't really understand: if I want to send data from an IP to my SOPC (in a BRAM), I need to make a MASTER IPIF which transfer the data to the BRAM. In the MASTER (PLB) IPIF, it takes the data and the address from my IP TEST with the ports Bus2IP and sends it to the BRAM with the ports IP2Bus. What is the aim of the IP2IP port ? When I want to send data to my BRAM, I send the address of the MASTER IPIF or of the BRAM ??? Thanks
Reply by ●April 16, 20072007-04-16
On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote:> "LilacSkin" <lpaul...@iseb.fr> wrote in message > > news:1176715616.959521.180000@b75g2000hsg.googlegroups.com... > > > Hi, > > I build a IPIF master with Create/Import Peripheral. > > I try the example write in the user_logic.vhd: > > volatile Xuint32* Data; > > Data=3D(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR; > > > // contr=F4l register > > Data=3D(Xuint32*)(0x00+0x00); > > *(Data)=3D0x40; > > You just overwrite your "Data" pointer. Unless XPAR_IPIF_MASTER_0_BASEADDR > is 0, you won't be accessing your peripheral. > > Didn't you mean > > Data=3D(Xuint32*)(XPAR_IPIF_MASTER_0_BASEADDR+0x00); > > ...and so on? > > -Ben-No change, when I want to store data from an IP to a BRAM, I send the data with an address to my Master PLB IPIF, but what is this address ? An address of the BRAM ??? The data and the address come from an IP TEST block. The IP TEST block is an IPIF ?? Tk very much
Reply by ●April 16, 20072007-04-16
"LilacSkin" <lpaulo07@iseb.fr> wrote in message news:1176723117.112802.254540@e65g2000hsc.googlegroups.com... On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote:> There is something i don't really understand: > if I want to send data from an IP to my SOPC (in a BRAM), I need to > make a MASTER IPIF which transfer the data to the BRAM. > In the MASTER (PLB) IPIF, it takes the data and the address from my IP > TEST with the ports Bus2IP and sends it to the BRAM with the ports > IP2Bus. > What is the aim of the IP2IP port ? > When I want to send data to my BRAM, I send the address of the MASTER > IPIF or of the BRAM ???I'm not sure I understood any of that... If you want to design a piece of IP that attaches to the rest of your system via a Coreconnect bus like PLB or OPB, then you have some options - it can be a bus slave, a bus master, or both. In fact, it might even have a master interface on one bus and a slave interface on another. The IPIF is supposed to make it easier for you to interface your IP to the Coreconnect bus, but you do not have to use it if you don't want to. If your IP is a bus master only, then it will be able to initiate its own transactions, but it will be inaccessible from the rest of the system. If it is a bus slave only, then it will be readable and writable from somewhere else (like your processor), but unable to initiate transactions. If it's both a master and a slave, then it has all these capabilities. The piece of code you posted seemed to be targetting a piece of IP with both a master and a slave interface. My understanding of it was that the processor would write some command registers to this IP, telling it what data to write and where to write it. Then when the IP is told to "go", it will perform its transaction on the PLB. In that case, you need to know where the IP's slave interface is mapped in memory, so that the processor can talk to it. It looks like XPAR_IPIF_MASTER_0_BASEADDR should be that address, but perhaps it is not. Sometimes when using the IPIF you need to access the peripherals "address range 0" base address instead - check to see what definitions are present in your xparameters.h file. Of course, a piece of IP like this is of no immediate practical use, because it would be just as easy for the processor to perform the transaction itself instead of going through this proxy. However, it's a useful exercise for getting to grips with the Coreconnect system and debugging your IP. You might also find it useful to attach a chipscope analyser to the PLB signals and watch what happens when your software runs. Good luck, -Ben-
Reply by ●April 16, 20072007-04-16
On 16 avr, 14:50, "Ben Jones" <ben.jo...@xilinx.com> wrote:> "LilacSkin" <lpaul...@iseb.fr> wrote in message > > news:1176723117.112802.254540@e65g2000hsc.googlegroups.com... > On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote: > > > There is something i don't really understand: > > if I want to send data from an IP to my SOPC (in a BRAM), I need to > > make a MASTER IPIF which transfer the data to the BRAM. > > In the MASTER (PLB) IPIF, it takes the data and the address from my IP > > TEST with the ports Bus2IP and sends it to the BRAM with the ports > > IP2Bus. > > What is the aim of the IP2IP port ? > > When I want to send data to my BRAM, I send the address of the MASTER > > IPIF or of the BRAM ??? > > I'm not sure I understood any of that... > > If you want to design a piece of IP that attaches to the rest of your system > via a Coreconnect bus like PLB or OPB, then you have some options - it can > be a bus slave, a bus master, or both. In fact, it might even have a master > interface on one bus and a slave interface on another. > > The IPIF is supposed to make it easier for you to interface your IP to the > Coreconnect bus, but you do not have to use it if you don't want to. > > If your IP is a bus master only, then it will be able to initiate its own > transactions, but it will be inaccessible from the rest of the system. If it > is a bus slave only, then it will be readable and writable from somewhere > else (like your processor), but unable to initiate transactions. If it's > both a master and a slave, then it has all these capabilities. > > The piece of code you posted seemed to be targetting a piece of IP with both > a master and a slave interface. My understanding of it was that the > processor would write some command registers to this IP, telling it what > data to write and where to write it. Then when the IP is told to "go", it > will perform its transaction on the PLB. In that case, you need to know > where the IP's slave interface is mapped in memory, so that the processor > can talk to it. It looks like XPAR_IPIF_MASTER_0_BASEADDR should be that > address, but perhaps it is not. Sometimes when using the IPIF you need to > access the peripherals "address range 0" base address instead - check to see > what definitions are present in your xparameters.h file. > > Of course, a piece of IP like this is of no immediate practical use, because > it would be just as easy for the processor to perform the transaction itself > instead of going through this proxy. However, it's a useful exercise for > getting to grips with the Coreconnect system and debugging your IP. > > You might also find it useful to attach a chipscope analyser to the PLB > signals and watch what happens when your software runs. > > Good luck, > > -Ben-thank you for your fast answer and your kindness, what i "just" want to do is access to a BRAM plugged to the PLB with an "external" IP, that why i want to build a MASTER PLB IPIF. i beging to understand how that system works thanks to the Xilinx sample but i have a problem with the address.
Reply by ●April 16, 20072007-04-16
I had to implement a PLB master the other year for a project. To be honest, it is actually easier if you just get the core connect spec and write it your self. In my case, I was only doing 64-bit transfers. The logic was actually pretty simple. I spent a week with the IPIF and it never really worked right. I told a co-worker that I did not think they ever tested the IPIF master operation. My own implementation only took a day or 2. Believe it or not the state machine to do is pretty small. LilacSkin wrote:> Hi, > > I build a IPIF master with Create/Import Peripheral. > I try the example write in the user_logic.vhd: > > -- Here's an example procedure in your software application to > initiate a 4-byte > -- write operation (single data beat) of this master model: > -- 1. write 0x40 to the control register > -- 2. write the source data address (local) to the ip2ip register > -- 3. write the destination address (remote) to the ip2bus > register > -- - note: this address will be put on the target bus address > line > -- 4. write 0x0004 to the length register > -- 5. write valid byte lane value to the be register > -- - note: this value must be aligned with ip2bus address > -- 6. write 0x0a to the go register, this will start the write > operation > > My C: > > #include "xparameters.h" > #include "xutil.h" > > int main (void) { > > volatile Xuint32* Data; > > Data=(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR; > > // contr�l register > Data=(Xuint32*)(0x00+0x00); > *(Data)=0x40; > > // source address > Data=(Xuint32*)(0x00+0x04); > *(Data)=XPAR_TEST_0_BASEADDR; > > //destination address > Data=(Xuint32*)(0x00+0x04); > *(Data)=XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR; > > // lengh register > Data=(Xuint32*)(0x00+0x04); > *(Data)=0x04; > > // BE register > Data=(Xuint32*)(0x00+0x02); > *(Data)=0xFF; > > // Go register > Data=(Xuint32*)(0x00+0x01); > *(Data)=0x0A; > > return 0; > } > > > I put one data in my TEST block, but nothing happened. > I want to transfer the data from the TEST block to a BRAM with this > IPIF, but i don't understand > what address i need to put in my TEST block to access to my BRAM. > > Can you help me ???? > Thanks >
Reply by ●April 16, 20072007-04-16
Eli Hughes wrote:> I had to implement a PLB master the other year for a project. To be > honest, it is actually easier if you just get the core connect spec and > write it your self. > > In my case, I was only doing 64-bit transfers. The logic was actually > pretty simple. I spent a week with the IPIF and it never really worked > right. I told a co-worker that I did not think they ever tested the > IPIF master operation. > > My own implementation only took a day or 2. Believe it or not the state > machine to do is pretty small.Eli, Just curious, did you debug it with HDL simulation or chipscope?
Reply by ●April 17, 20072007-04-17
Reply by ●April 17, 20072007-04-17
To build my PLB master, I only need that ports ??? PLB Master n Interface PLB-to-Master N PLB_MnWrDAck PLB_MnRdAck PLB_MnAddrAck PLB_MnRearbitrate PLB_MnTimeout Master n-to-PLB Mn_request Mn_priority(0:1) Mn_RNW Mn_size(0:3) Mn_rdBurst Mn_abort Mn_wrBurst Mn_ABus(0:31) Mn_UABus(0:31) PLB Slave n Interfaces PLB-to-slave n PLB_RNW PLB_abort PLB_wrBurst PLB_rdBurst PLB_masterID(0:2) PLB_PAValid PLB_SAValid PLB_ABus(0:31) PLB_UABus(0:31) Slave n-to-PLB PLB Sln_wait Sln_AddrAck Sln_rearbitrate Sln_rdComp Sln_rdDAck Sln_wrComp Sln_wrDAck Where are the ports in the IBM datasheet ? PLB_pendpri PLB_penreq PLB_reqpri PLB_size PLB_type PLB_rdPrim PLB_abort PLB_buslocked PLB_masterID PLB_MSize PLB_compress PLB_guarded PLB_lockerrr PLB_MErr, PLB_MBusy.......
