dual port memory from single port RAM.

Hi all,

My ASIC design requires dual port memories(one port R/W other port
only read) but there is a constraint on using it.
Instead I am planning to create this memory using single port RAM's.

Writes to this memory take place at 60 Mhz while reads can occur at
freq varying from 5-30 Mhz.

Is there some way out?

vlsi_learner wrote:
> Hi all,
> 
> My ASIC design requires dual port memories(one port R/W other port
> only read) but there is a constraint on using it.
> Instead I am planning to create this memory using single port RAM's.
> 
> Writes to this memory take place at 60 Mhz while reads can occur at
> freq varying from 5-30 Mhz.
> 
> Is there some way out?
> 
If you can allow waits on either port then you should be able to do 
this.  You would need an arbitrator that can detect when the memory is 
in use from one port and hold off the other port until the pending 
transaction is finished.  You'll need to be careful in your arbitrator 
design to make sure you don't have problems with requests coming in at 
the same time, and with your system design to make sure that the waits 
are OK.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details at http://www.wescottdesign.com/actfes/actfes.html

"vlsi_learner" <bajajk@gmail.com> writes:

> My ASIC design requires dual port memories(one port R/W other port
> only read) but there is a constraint on using it.
> Instead I am planning to create this memory using single port RAM's.

You an use two RAMs if you have enough RAM availabe in your
ASIC. Simply write into both RAMs using the same address and data.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

On Apr 16, 4:34 am, "vlsi_learner" <baj...@gmail.com> wrote:
> Hi all,
>
> My ASIC design requires dual port memories(one port R/W other port
> only read) but there is a constraint on using it.
> Instead I am planning to create this memory using single port RAM's.
>
> Writes to this memory take place at 60 Mhz while reads can occur at
> freq varying from 5-30 Mhz.
>
> Is there some way out?

At the very low write and read rates that you mention, just run the
memory at 120 MHz cycles, and use every even numbered period to write,
and the odd one to (potentially) read.
This may need  a little finesse if your reads are asynchronous, but
would otherwise be simple and economical.
Peter Alfke

Hi Petter,

I was trying to do the same, using 2 SPRAM's & writing to both of them
simultaneouly using same address & data.

addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr;    (port A is R/W port)

addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0);    (port B
is read only port)

In this case , if there is a write from port A then we cannot read
from the other port.Is this dual port
functionality?

Petter Gustad wrote:
> "vlsi_learner" <bajajk@gmail.com> writes:
>
> > My ASIC design requires dual port memories(one port R/W other port
> > only read) but there is a constraint on using it.
> > Instead I am planning to create this memory using single port RAM's.
>
> You an use two RAMs if you have enough RAM availabe in your
> ASIC. Simply write into both RAMs using the same address and data.
>
> Petter
> --
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?

In a dual-ported RAM, you have two independent access mechanism to the
common data, so you can read while you are writing. (In a "true dual-
ported RAM" you can also have two independent write, or two
independent read opertions going on simultaneously) But you still have
to avoid simultaneous read and write to the same location.
(Contention)
You avoid (almost) all these problem with Time-Division Multiplexing,
as I mentioned in my previous post.
Given your extremely slow speed, that's the way to go!
Peter Alfke


On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote:
> Hi Petter,
>
> I was trying to do the same, using 2 SPRAM's & writing to both of them
> simultaneouly using same address & data.
>
> addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr;    (port A is R/W port)
>
> addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0);    (port B
> is read only port)
>
> In this case , if there is a write from port A then we cannot read
> from the other port.Is this dual port
> functionality?
>

> Petter Gustad wrote:
> > "vlsi_learner" <baj...@gmail.com> writes:
>
> > > My ASIC design requires dual port memories(one port R/W other port
> > > only read) but there is a constraint on using it.
> > > Instead I am planning to create this memory using single port RAM's.
>
> > You an use two RAMs if you have enough RAM availabe in your
> > ASIC. Simply write into both RAMs using the same address and data.
>
> > Petter
> > --
> > A: Because it messes up the order in which people normally read text.
> > Q: Why is top-posting such a bad thing?
> > A: Top-posting.
> > Q: What is the most annoying thing on usenet and in e-mail?

Hi peter,

If I understand correctly, you are saying that I should use double
clock rate & then time multiplex the ports i.e
write on even clock into a single port RAM & read on the odd clock
from the SPRAM.
But what about reads at varying freq ( 5 - 30 Mhz)

Peter Alfke wrote:
> In a dual-ported RAM, you have two independent access mechanism to the
> common data, so you can read while you are writing. (In a "true dual-
> ported RAM" you can also have two independent write, or two
> independent read opertions going on simultaneously) But you still have
> to avoid simultaneous read and write to the same location.
> (Contention)
> You avoid (almost) all these problem with Time-Division Multiplexing,
> as I mentioned in my previous post.
> Given your extremely slow speed, that's the way to go!
> Peter Alfke
>
>
> On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote:
> > Hi Petter,
> >
> > I was trying to do the same, using 2 SPRAM's & writing to both of them
> > simultaneouly using same address & data.
> >
> > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr;    (port A is R/W port)
> >
> > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0);    (port B
> > is read only port)
> >
> > In this case , if there is a write from port A then we cannot read
> > from the other port.Is this dual port
> > functionality?
> >
>
> > Petter Gustad wrote:
> > > "vlsi_learner" <baj...@gmail.com> writes:
> >
> > > > My ASIC design requires dual port memories(one port R/W other port
> > > > only read) but there is a constraint on using it.
> > > > Instead I am planning to create this memory using single port RAM's.
> >
> > > You an use two RAMs if you have enough RAM availabe in your
> > > ASIC. Simply write into both RAMs using the same address and data.
> >
> > > Petter
> > > --
> > > A: Because it messes up the order in which people normally read text.
> > > Q: Why is top-posting such a bad thing?
> > > A: Top-posting.
> > > Q: What is the most annoying thing on usenet and in e-mail?

Hi Peter,

Another thing, what if I dont have the double clock available in the
design?

Thanks in advance for your help

vlsi_learner wrote:
> Hi peter,
>
> If I understand correctly, you are saying that I should use double
> clock rate & then time multiplex the ports i.e
> write on even clock into a single port RAM & read on the odd clock
> from the SPRAM.
> But what about reads at varying freq ( 5 - 30 Mhz)
>
> Peter Alfke wrote:
> > In a dual-ported RAM, you have two independent access mechanism to the
> > common data, so you can read while you are writing. (In a "true dual-
> > ported RAM" you can also have two independent write, or two
> > independent read opertions going on simultaneously) But you still have
> > to avoid simultaneous read and write to the same location.
> > (Contention)
> > You avoid (almost) all these problem with Time-Division Multiplexing,
> > as I mentioned in my previous post.
> > Given your extremely slow speed, that's the way to go!
> > Peter Alfke
> >
> >
> > On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote:
> > > Hi Petter,
> > >
> > > I was trying to do the same, using 2 SPRAM's & writing to both of them
> > > simultaneouly using same address & data.
> > >
> > > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr;    (port A is R/W port)
> > >
> > > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0);    (port B
> > > is read only port)
> > >
> > > In this case , if there is a write from port A then we cannot read
> > > from the other port.Is this dual port
> > > functionality?
> > >
> >
> > > Petter Gustad wrote:
> > > > "vlsi_learner" <baj...@gmail.com> writes:
> > >
> > > > > My ASIC design requires dual port memories(one port R/W other port
> > > > > only read) but there is a constraint on using it.
> > > > > Instead I am planning to create this memory using single port RAM's.
> > >
> > > > You an use two RAMs if you have enough RAM availabe in your
> > > > ASIC. Simply write into both RAMs using the same address and data.
> > >
> > > > Petter
> > > > --
> > > > A: Because it messes up the order in which people normally read text.
> > > > Q: Why is top-posting such a bad thing?
> > > > A: Top-posting.
> > > > Q: What is the most annoying thing on usenet and in e-mail?

My suggestion is you design for the worst case..... if u duplicate the
rams u will automatically get multiport reads....
you can create any multiples of frequencies from the DCM....

There are several ways to double a clock frequency.
Any Digital Clock Manager (DCM) orPLL will do it.
I published a very simple 1-flip-flop design on Xilinx  TechXclusives
("six easy pieces"), that assumes a 50% duty-cycle clock input.
A dual-ported RAM solves the problem of unrelated read and write
clocks, but not the potential problem of contention, when you write
to, and read from, the same location more or less simultaneously in an
asynchronous way. That's still your job to guard against.
But the time-division-multiplexed design that I recommended avoids
this problem altogether.
Peter Alfke

On Apr 17, 4:08 am, vlsi_learner <baj...@gmail.com> wrote:
> Hi Peter,
>
> Another thing, what if I dont have the double clock available in the
> design?
>
> Thanks in advance for your help
>
> vlsi_learner wrote:
> > Hi peter,
>
> > If I understand correctly, you are saying that I should use double
> > clock rate & then time multiplex the ports i.e
> > write on even clock into a single port RAM & read on the odd clock
> > from the SPRAM.
> > But what about reads at varying freq ( 5 - 30 Mhz)
>
> > Peter Alfke wrote:
> > > In a dual-ported RAM, you have two independent access mechanism to the
> > > common data, so you can read while you are writing. (In a "true dual-
> > > ported RAM" you can also have two independent write, or two
> > > independent read opertions going on simultaneously) But you still have
> > > to avoid simultaneous read and write to the same location.
> > > (Contention)
> > > You avoid (almost) all these problem with Time-Division Multiplexing,
> > > as I mentioned in my previous post.
> > > Given your extremely slow speed, that's the way to go!
> > > Peter Alfke
>
> > > On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote:
> > > > Hi Petter,
>
> > > > I was trying to do the same, using 2 SPRAM's & writing to both of them
> > > > simultaneouly using same address & data.
>
> > > > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr;    (port A is R/W port)
>
> > > > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0);    (port B
> > > > is read only port)
>
> > > > In this case , if there is a write from port A then we cannot read
> > > > from the other port.Is this dual port
> > > > functionality?
>
> > > > Petter Gustad wrote:
> > > > > "vlsi_learner" <baj...@gmail.com> writes:
>
> > > > > > My ASIC design requires dual port memories(one port R/W other port
> > > > > > only read) but there is a constraint on using it.
> > > > > > Instead I am planning to create this memory using single port RAM's.
>
> > > > > You an use two RAMs if you have enough RAM availabe in your
> > > > > ASIC. Simply write into both RAMs using the same address and data.
>
> > > > > Petter
> > > > > --
> > > > > A: Because it messes up the order in which people normally read text.
> > > > > Q: Why is top-posting such a bad thing?
> > > > > A: Top-posting.
> > > > > Q: What is the most annoying thing on usenet and in e-mail?