define variable in ISE9.1 Tcl scripts

Hi,

I've a question about ISE9.1 Tcl scripts. Is it possible to include
`define in Tcl project scripts to determine module to synthesize
according to `ifdef... `endif placed in the verilog sources ?

Thank you by advance,

Bests regards. Michel.

On 2007-04-17, michel.talon@gmail.com <michel.talon@gmail.com> wrote:
> Hi,
>
> I've a question about ISE9.1 Tcl scripts. Is it possible to include
> `define in Tcl project scripts to determine module to synthesize
> according to `ifdef... `endif placed in the verilog sources ?

I don't think xst accepts anything like -DCLOCKED=1 (as you can do in
the command line of most C-compilers). However, there are other ways
to do it. Lets say that you have a file test.v which contains the
following:

`ifdef CLOCKED
   always  @(posedge clk)  b <= a;
`else
   always @* b = a;
`endif

If you now want CLOCKED to be defined in test.v you can write a file
defines.v that contains `define CLOCKED and make sure that xst reads it
before any other file. CLOCKED will now be defined in all Verilog files
that are read after defines.v. (Unless it is explicitly undefined.)
Personally I think this behaviour of Verilog synthesizers is a bit
non-intuitive but IIRC it is specified that way in the Verilog standard.

You are going to have to think about how to keep your design and your
simulation in sync if you are going to do something like this though.

/Andreas