80000 Bit Shift Register

I am implementing an 80000 Element Shift register to be used as a very 
long (1Sec) digital delay generator. (Yes, its that big).     It is 
clocked at 80kHz.

Its a very simple design, just an ordinary shifter register with 80k 
elements. It is being implemented in a V2Pro (Digilent XUP Board).

I have simulated the design and it works OK.  I am now trying to 
synthesize the design and it is taking a *VERY* long time.  I tried to 
synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It 
failed 5 hours later with an out of memory error.  I am now trying on a 
Xeon Work station with 3GB of RAM.

Any pointers on how to make this synthesize faster?

What kind of machines are people using out there to synthesize large 
designs?

Eli Hughes wrote:
> 
> I am implementing an 80000 Element Shift register to be used as a very 
> long (1Sec) digital delay generator. (Yes, its that big).     It is 
> clocked at 80kHz.
> 
> Its a very simple design, just an ordinary shifter register with 80k 
> elements. It is being implemented in a V2Pro (Digilent XUP Board).
> 
> I have simulated the design and it works OK.  I am now trying to 
> synthesize the design and it is taking a *VERY* long time.  I tried to 
> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It 
> failed 5 hours later with an out of memory error.  I am now trying on a 
> Xeon Work station with 3GB of RAM.
> 
> Any pointers on how to make this synthesize faster?
> 
> What kind of machines are people using out there to synthesize large 
> designs?
> 


Here is my Code:

module shift(Clk, SIn, SOut);
     input Clk;
     input SIn;
     output SOut;


reg [80000:0] MyShift;
reg Out;

initial
begin
	MyShift = 0;
	Out=0;
end

assign SOut = Out;

always @(posedge Clk)
begin
	MyShift <= MyShift<<1;
	MyShift[0] <= SIn;
	//This is Needed to make XST happy and not reduce the design to
	//a GND net
	Out <= MyShift[80000];
end

endmodule

"Eli Hughes" <emh203@psu.edu> wrote in message 
news:f02jfc$nfi$1@f04n12.cac.psu.edu...
>
> I am implementing an 80000 Element Shift register to be used as a very 
> long (1Sec) digital delay generator. (Yes, its that big).     It is 
> clocked at 80kHz.
>
> Its a very simple design, just an ordinary shifter register with 80k 
> elements. It is being implemented in a V2Pro (Digilent XUP Board).
>
> I have simulated the design and it works OK.  I am now trying to 
> synthesize the design and it is taking a *VERY* long time.  I tried to 
> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It 
> failed 5 hours later with an out of memory error.  I am now trying on a 
> Xeon Work station with 3GB of RAM.
>
> Any pointers on how to make this synthesize faster?
>
> What kind of machines are people using out there to synthesize large 
> designs?
>
At 80 kHz, it would be easy to make a shift register out of the BRAMs if you 
aren't interested in the intermediate results. i.e. a FIFO. Each BRAM has 
18kbits. Search the Xilinx website for FIFO to see how to implement this.
HTH, Syms. 

Eli Hughes wrote:

> Any pointers on how to make this synthesize faster?

What about using block ram and just an index pointer? Shift-in: set current
bit at index, increment index pointer, read current bit and shift it out.
If the index pointer reaches some limit, reset it to 0. If you clock the
FPGA with a higher frequency, then the read/write cycles are no problem
with your shift clock.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Eli Hughes wrote:

> always @(posedge Clk)
> begin
> 	MyShift <= MyShift<<1;
> 	MyShift[0] <= SIn;
> 	//This is Needed to make XST happy and not reduce the design to
> 	//a GND net
> 	Out <= MyShift[80000];
> end

I don't know much about Verilog, but if you can use an index into the
MyShift register instead of actually shifting it, maybe your synthesize
program can infer a block ram automaticly.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Eli Hughes <emh203@psu.edu> writes:

> I am implementing an 80000 Element Shift register to be used as a
> very long (1Sec) digital delay generator. (Yes, its that big).  It
> is clocked at 80kHz.

At 80kHz you could probably get a 17-bit binary counter running. If
not you can use linear feedback shift register. 

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

"Eli Hughes" <emh203@psu.edu> wrote in message 
news:f02joe$nfq$1@f04n12.cac.psu.edu...
> Eli Hughes wrote:
>>
>> I am implementing an 80000 Element Shift register to be used as a very 
>> long (1Sec) digital delay generator. (Yes, its that big).     It is 
>> clocked at 80kHz.
>> Any pointers on how to make this synthesize faster?

I would use block RAM resources for the delay-line storage instead of FFs. 
That way you just need 5 RAM blocks per data bit, and a counter or two, 
rather than creating some massive power-hungry flip-flop spaghetti... :)

      -Ben- 

On Apr 17, 9:05 am, Frank Buss <f...@frank-buss.de> wrote:
> Eli Hughes wrote:
> > Any pointers on how to make this synthesize faster?
>
> What about using block ram and just an index pointer? Shift-in: set current
> bit at index, increment index pointer, read current bit and shift it out.
> If the index pointer reaches some limit, reset it to 0. If you clock the
> FPGA with a higher frequency, then the read/write cycles are no problem
> with your shift clock.
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

In the past, I had problems trying to get synthesis to build a memory
of std_logic types (i.e. a long std_logic_vector). To get around it I
declared an array of one bit std_logic_vectors, and that worked fine.

You might be able to declare an array of 80000 of those, and then use
a binary counter to read/write the memory. I've had synthesis tools
stitch together multiple ram primitives automatically in the past (in
depth and in width), but not that deep with block rams (never tried
it).

Sorry, my expertise is in vhdl, not verilog, but maybe you get the
idea anyway.

Andy

On 17 Apr., 15:52, Eli Hughes <emh...@psu.edu> wrote:
> I am implementing an 80000 Element Shift register to be used as a very
> long (1Sec) digital delay generator. (Yes, its that big).     It is
> clocked at 80kHz.
>
> Its a very simple design, just an ordinary shifter register with 80k
> elements. It is being implemented in a V2Pro (Digilent XUP Board).
>
> I have simulated the design and it works OK.  I am now trying to
> synthesize the design and it is taking a *VERY* long time.  I tried to
> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It
> failed 5 hours later with an out of memory error.  I am now trying on a
> Xeon Work station with 3GB of RAM.
>
> Any pointers on how to make this synthesize faster?
>
> What kind of machines are people using out there to synthesize large
> designs?

haven't checked if it actually works but it should be close,
synthesize in seconds infering 5 blockrams:

module shift(clk,in,out);

input clk,in;
output out;

reg out;

reg [80000:0] shiftreg;
reg [16:0]    index;

always@(posedge clk)
begin
	out <= shiftreg[index];
	shiftreg[index] <= in;
	if(index <17'd80000)
		index <= index +17'd1;
	else
		index <= 17'd0;

end


-Lasse

"Eli Hughes" <emh203@psu.edu> wrote in message 
news:f02jfc$nfi$1@f04n12.cac.psu.edu...
> I have simulated the design and it works OK.  I am now trying to 
> synthesize the design and it is taking a *VERY* long time.  I tried to 
> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It 
> failed 5 hours later with an out of memory error.  I am now trying on a 
> Xeon Work station with 3GB of RAM.
>
> Any pointers on how to make this synthesize faster?

I just tried Precision on your code and it took 10 minutes to synthesize on 
an AMD3500+ with 4Gbyte of memory. Compile took 400Mbyte, and synthesis 
1.4Gbyte (rough estimate from the task manager on Win2K).

Hans
www.ht-lab.com