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How to add customer peripheral with IP core to EDK?

Started by FPGA April 24, 2007
Hi All,

I am trying to add a customized OPB peripheral to the Microblaze
system in EDK/Platform Studio 8.1. My peripheral uses a FFT core
generated from Core Generator so it only comes with ngc netlist.

I instantiate the core in the user_logic.v. And I was able to
synthesize the peripheral using generated ISE project file by adding
the IP source file (core wizard) to the project. But when I add
peripheral to the system and generate the netlist, the XST tool always
complains: ERROR:HDLCompilers:87 - "D:\TechDrive\Project\Xilinx\AEC
\pcores\coproc_v1_00_a/hdl/verilog/user_logic.v" line 536 Could not
find module/primitive 'fft'

I did quite a bit search in the help,manual of EDK document,Core
Generator, XPS help but I could not find any help for such case.
Luckly I was able to find some help from this forum. One of them
suggests to add a bbd file and change mpd file in the core's
resposiories data folder. I tried exactly same step but it does not
work for me. I also tried to import the the peripheral to design
through both XST prj file and  PAO file but neither of them helps.

After spending two nights on this "intergration" issue without any
luck, I am pretty upset about the Xilinx tool chain especially the
document part! I thought this is very typical case(EDK->Peripheral-
>LogiCore) and there should be some sort of help easy for acess for
newbie. Maybe I am too blind to find it. But if somebody can point me out where the document is or workaround it through some tricky way, I'll greatly appreciate it! Thanks a lot! William
Can you please try copying the fft.ngc file produced by the core
generator into the implementation
sub-directory of  your EDK project directory and regenerate the
netlist ?

--swamy