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An Open-Source suggestion for Xilinx

Started by Antti May 8, 2007
On May 9, 4:00 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> In many ways the FPGA market is sluggish - they were very slow to move > from proprietary config memory, to industry std parts. > They are only on the first steps of waking up to, and using, > multi die design flows.
So sluggish, that reconfigurable computing may be completely dead shortly, unless these guys can open up in a big way. The presentation at FCCM by Los Alamos benchmarking performance, system, and development costs on FPGA, Cell, and GPU's left FPGA's dead last by a factor of 3 behind Cell performance and costs. While the work was done on a XC2VP50, a several year old product, as compared to a hot off the press Cell processor, is does show that Xiinx is close to losing high end applications where they have been a star ... and with that some serious high end revenue, rather than capitalizing on it's strengths while it still has a potential commodity market appeal, and using those dollars to refine that market penitration. While the Virtex 5 parts have significant promise, sluggish acceptance of the market will certainly kill it, as will the high prices from low volumes that can easily be corrected by facilitating acceptance as a comodity and supporting the market properly for these applications.
Herbert Kleebauer wrote:
> What would you say, if a CPU manufacturer doesn't make available > the processor documentation (instruction set, instruction encoding). > He only gives you a C compiler to design your software and > anything below is the secret of the company.
It's been done. The "Neuron" processor that Motorola and Toshiba made for Lonworks. It looked like it would be a good chip for some of my designs at the time, but since the instruction set, etc. was secret, I decided against using it, as did other engineers I knew.
> Nobody would buy such a processor, > but that's exactly the situation with FPGA's.
Obvioiusly some people would buy such a processor, since some did. The situation with FPGAs is more complex. Most people don't even want to know the details of the bitstream, and are satisfied with proprietary tools.
fpga_toys@yahoo.com wrote:

> On May 9, 4:00 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > >>In many ways the FPGA market is sluggish - they were very slow to move >>from proprietary config memory, to industry std parts. >>They are only on the first steps of waking up to, and using, >>multi die design flows. > > > So sluggish, that reconfigurable computing may be completely dead > shortly, unless these guys can open up in a big way. The presentation > at FCCM by Los Alamos benchmarking performance, system, and > development costs on FPGA, Cell, and GPU's left FPGA's dead last by a > factor of 3 behind Cell performance and costs.
How did the GPUs stack up in this comparison ?
> While the work was > done on a XC2VP50, a several year old product, as compared to a hot > off the press Cell processor, is does show that Xiinx is close to > losing high end applications where they have been a star ... and with > that some serious high end revenue, rather than capitalizing on it's > strengths while it still has a potential commodity market appeal, and > using those dollars to refine that market penitration. > > While the Virtex 5 parts have significant promise, sluggish acceptance > of the market will certainly kill it, as will the high prices from low > volumes that can easily be corrected by facilitating acceptance as a > comodity and supporting the market properly for these applications.
FPGA sales growth is not stellar, and if you compare them with the fabless averages, FPGAs are pulling down the numbers. High speed serial links do seem to be one area FPGAs can have a safe niche. Altera ahve new devices there, as do Lattice. - so you might find a system designed with (many) Cell processors, liked with FPGA Serial backplanes, could be the best pathway for reconfigurable computing ? -jg
Antti <Antti.Lukats@xilant.com> wrote:
>Stephen Williams schrieb: >> -----BEGIN PGP SIGNED MESSAGE----- >> >> Where I work, we've pretty much given up on being able to use >> impact for anything other then writing ACE files, and it does >> a clunky job at that. I suspect that open-sourcing impact would >> make a *lot* of folks very very happy. >Hi Steve
>I just recalled, I have reverse engineered the ACE file format >even written ACE compressor and player, so the work has begun >already :)
>ah, yes I can open-source the ACE player.. please remind in a few days >should i forget..
Isn't ACE just a compression algorithm/format..?
On 13 Mai, 12:00, pbF...@ludd.invalid wrote:
> Antti <Antti.Luk...@xilant.com> wrote: > >Stephen Williams schrieb: > >> -----BEGIN PGP SIGNED MESSAGE----- > > >> Where I work, we've pretty much given up on being able to use > >> impact for anything other then writing ACE files, and it does > >> a clunky job at that. I suspect that open-sourcing impact would > >> make a *lot* of folks very very happy. > >Hi Steve > >I just recalled, I have reverse engineered the ACE file format > >even written ACE compressor and player, so the work has begun > >already :) > >ah, yes I can open-source the ACE player.. please remind in a few days > >should i forget.. > > Isn't ACE just a compression algorithm/format..?
I mean the "Xilinx ACE", file format for SystemACE its sort of JTAG bytecode, and the information is not public its very simple code, and player is very simple too, way simpler than jam or xsvf... Antti
On May 8, 4:34 am, Antti <Antti.Luk...@xilant.com> wrote:
> 1) Impact TCP protocol has been reverse engineered > and there is open-source cable-server > 2) I have tried to make software support for Cable IV high > speed mode, even made special FPGA-PCI design that emulates > LPT port + Cable IV. There is no final result on that yet. > 3) I have written Coolrunner disassembler in order to reverse > engineer the Cable IV code > 4) There is 3rd party replacement firmware for USB platform cable > 5) possible more projects that we dont know about.
The biggest problem with much of this, is a mine field caused by the Xilinx NDA in their software license, combined with US copyright laws (slightly mitigated by EU restrictions), especially where any form of encryption is used for protection. Some open source projects have openly ignored the legal reverse engineering standards, requiring independent teams to write functional specifications and do the implementation from those clean room specifications without knowledge of the original implementation details and coding. Failure to do so. leaves the reverse engineered (rewritten) product contaminated or tainted, and a derivative work. These legal standards for reverse engineering were set by years of litigation by major corporations, and set a very clear line in the sand about what is, and is not, legal ... right down to hiring workers which have detailed inside knowledge of a product and what that worker can do at a new employers shop. In the US, such reverse engineering failures can result in significant legal judgements, and/or possible jail where encryption algorithms are concerned, or risk of flight exists to avoid court proceedings. Even if you live abroad, entry into the US after such violations, can leave you in jail, if US laws are applied to you when you enter. Selling products which violate Xilinx IP rights, or giving them away as open source, will give Xilinx the power to pick and choose who they wish to enforce their rights against. The Xilinx software NDA terms are very broad, so if the information you use for the reverse engineering is included in their software products, watch out ... carefully follow both the US and EU laws. It's this simple problem of Xilinx NDA and license terms that makes the company very very high risk to support with open source development. They include/use major Open Source products freely, but then hide behind these very strict NDA and License terms to protect everything from documentation, algorithms, to data formats from being used openly for open source development to support their product line. We've had this discussion several times in this forum. John
The legal requirements for reverese engineering date back to 1970's
and 1980's. Big name successes were clean-room reverse engineering of
the BIOS for the IBM PC by Compaq and Pheonix in the early 1980's, and
AMD's clean room versions of Intel Microcode. See

http://en.wikipedia.org/wiki/Clean_room_design
http://en.wikipedia.org/wiki/Compaq_Computer_Corporation
http://software.newsforge.com/article.pl?sid=06/02/01/1630225&tid=132&tid=25
http://en.wikipedia.org/wiki/Advanced_Micro_Devices

As a result, we frequently see license terms which completely bar
reverse-engineering, so even where it might be completely legal
otherwise, such as areas outside the US, the legal contract created by
the license and NDA extends the protections in ways that can result in
civil and criminal litigation. In places where the legal protections
are lacking, it's quite common to see licenses which specifically
prevent it's sale into those regions, holding the seller/buyer at risk
under US law.

On May 9, 6:07 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> How did the GPUs stack up in this comparison ?
Sorry, miss place my copy of the proceedings ... here are a few points from the paper presented at FCCM 4/24/07 by Los Alamos Labs: "Matched Filter Computation on FPGA, Cell, GPU", by Zachary Baker, Maya Gokhale, and Justin Tripp. Implementation Speedup Cost Power Speedup/$K Speedup/kWatt Cray XD1/2VP50 3.91 $10K 350W 0.39 11.2 Nvidia GeForce 7900 3.10 $2.6K 350W 1.24 8..7 IBM Cell Processor 8.0 $8K 315W 1.0 25.4 This table is normalized to a reference CPU. The authors presentation provided a great wealth of comparitive development cost issues not presented in the paper, where the FPGA and GPU didn't fare well ... lack of tools and internals documention for optimization. With the Cell processor going commodity, it is very likely to take over numerical applications where FPGA's previously had leadership ... such as DSP. I still believe the FPGA's have a good market ... if large FPGA's can leverage commodity pricing combined with excellent low cost license free tools. Since this is a completely different market, with very different expectations, it's unlikely the existing vendors tools team can/will provide the tools. They are still focused on what hardware designers need, not large scale programmer lead teams that are certainly NOT going to code in VHDL. With the cost of electricity soaring with energy cost increases, we are already seeing $0.36/KWH in some places. So Super Computer faciities that are tens of megawatts are seeing cost of ownership hinge on power and cooling costs.
fpga_toys@yahoo.com wrote:
> On May 9, 6:07 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > >>How did the GPUs stack up in this comparison ? > > > > Sorry, miss place my copy of the proceedings ... here are a few points > from the paper presented at FCCM 4/24/07 by Los Alamos Labs: "Matched > Filter Computation on FPGA, Cell, GPU", by Zachary Baker, Maya > Gokhale, and Justin Tripp. > > Implementation Speedup Cost Power > Speedup/$K Speedup/kWatt > Cray XD1/2VP50 3.91 $10K 350W > 0.39 11.2 > Nvidia GeForce 7900 3.10 $2.6K 350W > 1.24 8..7 > IBM Cell Processor 8.0 $8K 315W > 1.0 25.4 > > This table is normalized to a reference CPU. The authors presentation > provided a great wealth of comparitive development cost issues not > presented in the paper, where the FPGA and GPU didn't fare well ... > lack of tools and internals documention for optimization. With the > Cell processor going commodity, it is very likely to take over > numerical applications where FPGA's previously had leadership ... such > as DSP. > > I still believe the FPGA's have a good market ... if large FPGA's can > leverage commodity pricing combined with excellent low cost license > free tools. Since this is a completely different market, with very > different expectations, it's unlikely the existing vendors tools team > can/will provide the tools. They are still focused on what hardware > designers need, not large scale programmer lead teams that are > certainly NOT going to code in VHDL. > > With the cost of electricity soaring with energy cost increases, we > are already seeing $0.36/KWH in some places. So Super Computer > faciities that are tens of megawatts are seeing cost of ownership > hinge on power and cooling costs.
Thanks - interesting numbers. -jg
Antti wrote:

> On 13 Mai, 12:00, pbF...@ludd.invalid wrote: > >>Antti <Antti.Luk...@xilant.com> wrote: >> >>>Stephen Williams schrieb: >>> >>>>-----BEGIN PGP SIGNED MESSAGE----- >> >>>>Where I work, we've pretty much given up on being able to use >>>>impact for anything other then writing ACE files, and it does >>>>a clunky job at that. I suspect that open-sourcing impact would >>>>make a *lot* of folks very very happy. >>> >>>Hi Steve >>>I just recalled, I have reverse engineered the ACE file format >>>even written ACE compressor and player, so the work has begun >>>already :) >>>ah, yes I can open-source the ACE player.. please remind in a few days >>>should i forget.. >> >>Isn't ACE just a compression algorithm/format..? > > > I mean the "Xilinx ACE", file format for SystemACE > its sort of JTAG bytecode, and the information is not public > > its very simple code, and player is very simple too, > way simpler than jam or xsvf...
Hi Antti, A simpler bytecode/compression scheme sounds like something that would benefit everyone ? So, this is the requested reminder, after a few days, to open source this :) I'd also cc Xilinx, and say this has wide industry support. They could take a lead from Lattice - they are getting good PR mileage from their Open Sourced SoftCPUs. If I were in Xilinx, I'd sponser a web site for this stuff. It's cheaper than $$$ advertising, and it really does help burnish a tarnished image. Xilinx ? -jg