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does SRL exist in non-xilinx FPGAs?

Started by Unknown May 14, 2007
Hey,

Is there any non-xilinx FPGA that has the equivalent of Xilinx Virtex
SRL component as a basic component logic? If Not, why? has Xilinx
patented it?

Many Thanks  :)

?

Xilinx has patents on the use of a LUT as a LUT, SRL, or LUTRAM (by
configuration).  This is presumably broad enough that others have
decided not to try to "design around" the patents, but have rather
decided to provide similar function through other means.

There is nothing to prevent someone from inserting a shift register in
their logic block as a completely separate element.  They just are not
able to use the LUT bits to perform the function (as that is one of our
basic claims).

FPGA repeatable interconnect structure with hierarchical interconnect
lines US Pat. 5914616 - Filed Feb 26, 1997 - XILINX, Inc.
When function generators F, G, H, J are configured as shift registers as
described by Bauer, the shift register data input signal is taken from
BF, BG, BH, ...

FPGA architecture with deep look-up table RAMs
US Pat. 6288568 - Filed May 19, 2000 - Xilinx, Inc.
11 12 historically paired with flip-flops in Xilinx logic elements.
location in a shift register and all other data are shifted one Further,
when an n-bit, ...

Linear feedback shift register in a programmable gate array
US Pat. 6181164 - Filed May 13, 1999 - Xilinx, Inc.
Before data is fed back into the gates as shown and which can be
implemented with a shift register, parity must have been generated from
all the 4-LUT. ...

Structure for optionally cascading shift registers US Pat. 6118298 -
Filed Feb 18, 1999 - Xilinx, Inc. first full 16-bit shift register 1200
addressed to 1111, a second full ... 8 provides only a single output
from each LUT, (outputs are labeled X and Y), ...

FPGA repeatable interconnect structure with bidirectional and
unidirectional interconnect lines US Pat. 5942913 - Filed Mar 20, 1997 -
Xilinx, Inc. For example, pages 4-11 through 4-23 of the Xilinx 1996
Data Book ... the shift register data input signal is taken from BF, BG,
BH, BJ, respectively. ...

Configurable logic element with ability to evaluate five and six input
functions US Pat. 5920202 - Filed Apr 4, 1997 - Xilinx, Inc.
The function generator of this embodiment can therefore be configured as
a look-up table, a shift register, a 16x1 RAM, half of a 16x1
dual-ported RAM (when ...

FPGA lookup table with speed read decoder US Pat. 6529040 - Filed May 5,
2000 - Xilinx, Inc. In addition to the configuration mode and memory
read/ write operations, LUT 300 can implement a shift register. During
shift register operations, ...

FIFO in FPGA having logic elements that include cascadable shift
registers US Pat. 6262597 - Filed Jul 24, 2000 - Xilinx, Inc.
If a shift register FIFO is desired that is no more than 16 words deep,
then such a 10 the right of the picture, for example cell 77016 of LUT-F
of slice ...

FPGA lookup table with dual ended writes for ram and shift register
modes US Pat. 6373279 - Filed May 5, 2000 - Xilinx, Inc.
In addition to the configuration mode and memory read/ write operations,
LUT 300 can implement a shift register. During shift register
operations, ...

(above from google patents).

The oldest patents are from 1997, so they have a while yet before they
expire.

Next time you have a question like this, try google patent!

http://www.google.com/patents

Austin