xilinx 70% tracking rule

Hi there,

Sorry for another Xilinx-specific question :)

Peter Alfke mentioned this 70% tracking rule for timing parameters,
which basically says that if a parameter is at its max value, then all
other parameters are between 70% and 100% of their guaranteed maximums.
For Xilinx CPLDs, at least.

This makes a lot of sense from a physical standpoint, and I've seen
it mentioned in other posts too.

I have only one question, if somebody can help. How is this 70% figure
calculated, or estimated? Is it based on lab results only, or was it
first derived analytically in some way or another and then verified
experimentally? (I believe the latter). I'm curious about the physics
involved.

Thanks,
Guillermo Rodriguez

guille wrote:

> Hi there,
> 
> Sorry for another Xilinx-specific question :)
> 
> Peter Alfke mentioned this 70% tracking rule for timing parameters,
> which basically says that if a parameter is at its max value, then all
> other parameters are between 70% and 100% of their guaranteed maximums.
> For Xilinx CPLDs, at least.
> 
> This makes a lot of sense from a physical standpoint, and I've seen
> it mentioned in other posts too.
> 
> I have only one question, if somebody can help. How is this 70% figure
> calculated, or estimated? Is it based on lab results only, or was it
> first derived analytically in some way or another and then verified
> experimentally? (I believe the latter). I'm curious about the physics
> involved.

It will be experimental / empirical.
It derives from all gates being on the same wafer (thus largely process 
track), and at the same Vcc, and similar Temperatures.
Normal process tracking these days is very good, and a portion of
variance will be physical location dependant, but it's easier to
umbrella that under process or min/max timing.

-jg

I don't know whether 70% is the correct number or not, as it depends on many
things and on how sophisticated the timing model was for the "maximum"
numbers in the first place.  But here are a few other phenomena to add to
the laundry list:
- Differences between rising and falling delay (is the max # worst case of
two?)
- Localized IR drop in power network causes differences in Vdd seen by
transistors in different areas of chip
- Temperature gradients due to differing power densities
- Unmodeled differences in physical structure between similar resources.
For example, in a crude timing model all wires of length 4 could be given
same delay, but in reality there are differences in what metal they are
adjacent to, they could have slightly different lengths, etc.  Or trace
lengths for two IOs could be slightly different.  Of course, whether this
need be included in the 70% depends on whether timing model accounts for
this stuff or not.
- Cross-coupling, which can speed up (or slow down) a signal.

Also, some aspects of process track very well across a die (e.g. metal,
dielectric thickness), while others do not -- for example, tranistor
threshold voltage can vary significantly from one transistor to the next due
to the stoicastic nature of implants/dopants, though the average Vt value
will be similar across the die.  Since timing paths include multiple
transistors, you tend to get an averaging effect, but still, it is another
thing to worry about.

But this is why FPGA companies have timing modeling and characterization
groups, and part of why FPGAs are slowly taking over the world (or so I hope
:-) -- imagine having to worry about all this stuff when doing your ASIC?

Regards,

Paul Leventis
Altera Corp.


> It will be experimental / empirical.
> It derives from all gates being on the same wafer (thus largely process
> track), and at the same Vcc, and similar Temperatures.
> Normal process tracking these days is very good, and a portion of
> variance will be physical location dependant, but it's easier to
> umbrella that under process or min/max timing.

"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<7gKPb.46671$lGr.8430@twister01.bloor.is.net.cable.rogers.com>...
> I don't know whether 70% is the correct number or not, as it depends on many
> things and on how sophisticated the timing model was for the "maximum"
> numbers in the first place.  But here are a few other phenomena to add to
> the laundry list:
[...]

Interesting! Thanks for your input.

This 70% figure was for Xilinx CPLDs. What would be a good estimation
for Altera devices?

Does Altera document tracking properties for their devices? (either
'officially' in datasheets, or in application notes). Just curious.

> 
> But this is why FPGA companies have timing modeling and characterization
> groups, and part of why FPGAs are slowly taking over the world (or so I hope
> :-) -- imagine having to worry about all this stuff when doing your ASIC?

I can imagine :)

Guillermo Rodriguez

"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<7gKPb.46671$lGr.8430@twister01.bloor.is.net.cable.rogers.com>...
...
> 
> But this is why FPGA companies have timing modeling and characterization
> groups, and part of why FPGAs are slowly taking over the world (or so I hope
> :-) -- imagine having to worry about all this stuff when doing your ASIC?

Yes, imagine working with a part that comes with a data
sheet with 100% clearly defined timing for each cell !
Just open the data sheet and get 100% clear information.

(Routing delays are undefined until Synthesis and P&R for both.)

> Regards,
> 
> Paul Leventis
> Altera Corp.

This BS marketing from FPGA companies is 80% nonsenseand
5% Truth. The remaining 15% are pure lies.

Regards,
rudi
========================================================
   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Strong words, Rudi !
But unless you can substantiate your claims, we will ignore them as your
kind of BS.
I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.
For some reason the world is rapidly converting to FPGA. Last year there
were less than 1500 new ASIC designs and probably 100 000  new designs
using FPGAs. Many of us in this ng are aware of the ASIC advantages, but
they come with a hefty price tag, long manufacturing time, risk and
inflexibility. That's why most of us prefer FPGAs. It is also reflected
in the name of this ng.

So, Rudi, if you want to post here, say something meaningful, and do not
just blurt out unsubstantiated insults. Hurts your reputation more than mine...

Peter Alfke,     
============================================
Rudolf Usselmann wrote:
>
> This BS marketing from FPGA companies is 80% nonsenseand
> 5% Truth. The remaining 15% are pure lies.
> 
> Regards,
> rudi
> ========================================================
>    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> ..............::: FPGAs * Full Custom ICs * IP Cores :::
> FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Peter Alfke wrote:
> 
> Strong words, Rudi !
> But unless you can substantiate your claims, we will ignore them as your
> kind of BS.
> I am an engineer, and I do not make marketing claims, and neither do I
> publish 80% nonsense and 15% lies.

I am not looking to get into this argument, but certainly there are lies
that marketing tells.  I caught Linear Tech in an outright lie in an ad
that claimed a switcher could be built in a certain amount of board
space.  I called and asked for info on that design and was told that
there *was no design*.  It was a number that no one could even explain
how they came up with.  

Closer to home is the ever present lie in the Xilinx data sheets about
logic cell count.  The last time I checked, counting involved actually
counting things.  Xilinx seems to think that counting logic cells
involves counting and then multiplying by 1.125.  

This may be a small case, but so much of what semi companies put out in
ads and in literature is clearly hyped.  You may not like it as an
engineer, but it is the truth.

Ralph, you don't find me quoting those "12% inflated" numbers.
I hate thatfake arithmetic, but I have at times explained the reasoning
behind it, without endorsing it. It seems to be a trap without an easy
exit. Hell, we don't need those lousy 12.5% to look good. This is stuff
from a bygone era.
Anyhow, this does not make it "80% nonsense and 15% lies".
I have a right to defend myself and my company against silly
accusations.  We don't have to agree always, but we need not accept insults.

Peter Alfke
=========================================
Ralph Malph wrote:
> 
>  
> Closer to home is the ever present lie in the Xilinx data sheets about
> logic cell count.  The last time I checked, counting involved actually
> counting things.  Xilinx seems to think that counting logic cells
> involves counting and then multiplying by 1.125.
> 
> This may be a small case, but so much of what semi companies put out in
> ads and in literature is clearly hyped.  You may not like it as an
> engineer, but it is the truth.

Wow, a real flame war at comp.arch.fpga.

Rudi: I guess from your asic design experience you can guess, why the
timing for routing is not well defined before the routing is done.

But mostly I am posting as a response to Peter:
Success of a product does not actually contradict overly optimistic
marketing claims. At least short time success should be able to be
improved by marketing lies, don't you think?

You should not be offended personally. You now that the information
from you and austin is always better and more detailed and often very
different from what's in datsheets let alone the press releases.
So if a lot of people dislike the press releases, this does not mean,
they do not respect you. And many of them use Xilinx, so they do not
think to bad of the product either.

But there is reason not to like Xilinx marketing.

Remember the press release that claimed prices that are valid NOW but
not before Q4/2004? I do not use "now" that way.
Or Insight who send me spam that told me I could get XC3S200 in volume
now but at the phone told me I could not even get samples?
 
The problem for us engineers is, that our customers read the press
releases.
And we always look like idiots when we have to explain them, that we
can not do that what Xilinx suggests. Or not yet. Or only at 20x the
price. Or only if they buy a million parts.

Regards,

Kolja


Peter Alfke <peter@xilinx.com> wrote in message news:<401011AA.9D090355@xilinx.com>...
> Strong words, Rudi !
> But unless you can substantiate your claims, we will ignore them as your
> kind of BS.
> I am an engineer, and I do not make marketing claims, and neither do I
> publish 80% nonsense and 15% lies.
> For some reason the world is rapidly converting to FPGA. Last year there
> were less than 1500 new ASIC designs and probably 100 000  new designs
> using FPGAs. Many of us in this ng are aware of the ASIC advantages, but
> they come with a hefty price tag, long manufacturing time, risk and
> inflexibility. That's why most of us prefer FPGAs. It is also reflected
> in the name of this ng.
> 
> So, Rudi, if you want to post here, say something meaningful, and do not
> just blurt out unsubstantiated insults. Hurts your reputation more than mine...
> 
> Peter Alfke,     
> ============================================
> Rudolf Usselmann wrote:
> >
> > This BS marketing from FPGA companies is 80% nonsenseand
> > 5% Truth. The remaining 15% are pure lies.
> > 
> > Regards,
> > rudi
> > ========================================================
> >    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> > ..............::: FPGAs * Full Custom ICs * IP Cores :::
> > FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

> Ralph Malph wrote:

>>logic cell count.  The last time I checked, counting involved actually
>>counting things.  Xilinx seems to think that counting logic cells
>>involves counting and then multiplying by 1.125.

Why would an engineer be concerned
about such estimates when he can run a
synthesis on his design and
get the *exact utilization* ?

         -- Mike Treseler