SERDES question (Lattice ispHSI)

Hi!

I need to design a simple serializer/deserializer as part of my bigger
experimental project. I've started with reading various application notes
from Lattice, Xilinx and Altera, as I don't feel very comfortable with
multiple clock domain designs, nor with very high speed clocks in general. 

I've found one slightly confusing sketch in Lattice app. note, available
here http://www.latticesemi.com/lit/docs/technotes/tn1020.pdf 

Figure 5 shows a basic serializer. My understanding:
- 'LS Clock' is derived by dividing HSTCLK by n, so both clocks are in phase
- 'Align' block is clocked with HSTCLK and it asserts 'Parallel Load' output
for  one HSTCLK period, when it detects rising edge of 'LS Clock'
- looking at serializer timing diagrams (p. 27) I can see that output (and
thus parallel load) is delayed by 2 HSTCLK cycles, which confirms my
understanding so far

Q: Given all that - why do we need 'Parallel Sync Register' ? Parallel load
to Shift Register is delayed by 2 HSTCLK cycles from 'LS Clock' rising
edge, so 'Parallel Load Register' outputs have enough time to settle. 

Where is my misunderstanding?

Best Regards,
Przemek 

Are you using this for a source synchronous application?

Thanks.

CP

On May 16, 9:50 pm, Test01 <cpan...@yahoo.com> wrote:
> Are you using this for a source synchronous application?

Yes, however at that time I'm only looking at the serializer, let's
leave deserializer for a moment.

My final implementation will not use any specialized blocks (I'm about
to use Spartan-3). I just want to understand why do they need this
extra (in my opinion) register in the serializer block. I'm just
learning from exisitng solutions :)

Best Regards,
Przemyslaw