Timing not met but working on board

Hi all,
I developed a design in which i need a master clock of 90Mhz, so
during synthesis max. freq obtained is 56Mhz and  timing is met for
global clock of 50Mhz, but timing are not met for 90Mhz.
but design is working on board for 90Mhz clcock.
In design all lower level module are working above 100 Mhz, but in top
module after integarting sub blocks it works around 56 Mhz in
synthesis and working at 90Mhz on board.
so please tell me what is wrong with this design.
Regards
J.Ram

On May 21, 1:52 pm, "J.Ram" <jrgod...@gmail.com> wrote:
> Hi all,
> I developed a design in which i need a master clock of 90Mhz, so
> during synthesis max. freq obtained is 56Mhz and  timing is met for
> global clock of 50Mhz, but timing are not met for 90Mhz.
> but design is working on board for 90Mhz clcock.
> In design all lower level module are working above 100 Mhz, but in top
> module after integarting sub blocks it works around 56 Mhz in
> synthesis and working at 90Mhz on board.
> so please tell me what is wrong with this design.
> Regards
> J.Ram

It may be because u are not yet applied any test vectors which will
violate the 50MHz+ timings..... That may be the one reason why it is
working on the board....

Un bel giorno J.Ram digit�:

> but timing are not met for 90Mhz.
> but design is working on board for 90Mhz clcock.

As far as I know, the timing extimations in ISE are made assuming always
the worst case scenario (worst temperatures, worst limit of each specified
parameter, etc). They represent a "lower performance limit", but for the
actual speed limit I've noticed a lot of difference between the extimation
and the reality, especially in blocks with few gates. For example in a
SpartanII design I have a 8-bit gray counter incremented by an external
clock that in reality exceeds 250 MHz of performance, while the timing
extimations suggest a maximum frequency that barely exceeds 100 MHz.

-- 
emboliaschizoide.splinder.com

"J.Ram" <jrgodara@gmail.com> wrote in message 
news:1179737574.032115.244360@a26g2000pre.googlegroups.com...
> Hi all,
> I developed a design in which i need a master clock of 90Mhz, so
> during synthesis max. freq obtained is 56Mhz and  timing is met for
> global clock of 50Mhz, but timing are not met for 90Mhz.
> but design is working on board for 90Mhz clcock.
> In design all lower level module are working above 100 Mhz, but in top
> module after integarting sub blocks it works around 56 Mhz in
> synthesis and working at 90Mhz on board.
> so please tell me what is wrong with this design.
> Regards
> J.Ram

What is wrong is your expectation that based on a sample of one board that 
works at 90 MHz, that all boards over all rated temperature conditions over 
all possible input conditions will also work at that speed.

It's not at all unusual to expect that a single board in a lab environment 
might happen to work at ~50% over the speed computed by the timing analyzer. 
Try building thousands of such boards and put them in the extreme rated 
temperature conditions and give them the most stressful input pattern and 
see how many of those boards still work.  What you'll likely find is a lot 
of fallout...but again you might have a few survivors.

KJ 

On May 21, 4:20 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "J.Ram" <jrgod...@gmail.com> wrote in message
>
> news:1179737574.032115.244360@a26g2000pre.googlegroups.com...
>
> > Hi all,
> > I developed a design in which i need a master clock of 90Mhz, so
> > during synthesis max. freq obtained is 56Mhz and  timing is met for
> > global clock of 50Mhz, but timing are not met for 90Mhz.
> > but design is working on board for 90Mhz clcock.
> > In design all lower level module are working above 100 Mhz, but in top
> > module after integarting sub blocks it works around 56 Mhz in
> > synthesis and working at 90Mhz on board.
> > so please tell me what is wrong with this design.
> > Regards
> > J.Ram
>
> What is wrong is your expectation that based on a sample of one board that
> works at 90 MHz, that all boards over all rated temperature conditions over
> all possible input conditions will also work at that speed.
>
> It's not at all unusual to expect that a single board in a lab environment
> might happen to work at ~50% over the speed computed by the timing analyzer.
> Try building thousands of such boards and put them in the extreme rated
> temperature conditions and give them the most stressful input pattern and
> see how many of those boards still work.  What you'll likely find is a lot
> of fallout...but again you might have a few survivors.
>
> KJ

Can we say that is ~50%....

J.Ram wrote:
> Hi all,
> I developed a design in which i need a master clock of 90Mhz, so
> during synthesis max. freq obtained is 56Mhz and  timing is met for
> global clock of 50Mhz, but timing are not met for 90Mhz.
> but design is working on board for 90Mhz clcock.
> In design all lower level module are working above 100 Mhz, but in top
> module after integarting sub blocks it works around 56 Mhz in
> synthesis and working at 90Mhz on board.
> so please tell me what is wrong with this design.
> Regards
> J.Ram

It's not the *entire* chip that's limited to 56 MHz.  Use the Xilinx 
Timing Analyzer to determine which paths are failing timing.  This will 
both inform you as to where you might see the failure show up (e.g., if 
it's an accumulator to a register read by software, you'll only know 
it's a problem if you know what the count should be when/if you read 
it).  It will also give you an idea of where to recode your RTL to 
achieve 100% timing.

On 21 Mai, 13:18, dalai lamah <antonio12...@hotmail.com> wrote:
> Un bel giorno J.Ram digit=F2:
>
> > but timing are not met for 90Mhz.
> > but design is working on board for 90Mhz clcock.
>
> As far as I know, the timing extimations in ISE are made assuming always
> the worst case scenario (worst temperatures, worst limit of each specified
> parameter, etc). They represent a "lower performance limit",

True.
Another aspect is that static timing analysis is pessimistic. The
slowest path
reported might be a path that is never switching in the design
scenario at hand
or even can't switch under any circumstances (false path).

Kolja Sulimma

On May 21, 6:20 am, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "J.Ram" <jrgod...@gmail.com> wrote in message
>
> news:1179737574.032115.244360@a26g2000pre.googlegroups.com...
>
> > Hi all,
> > I developed a design in which i need a master clock of 90Mhz, so
> > during synthesis max. freq obtained is 56Mhz and  timing is met for
> > global clock of 50Mhz, but timing are not met for 90Mhz.
> > but design is working on board for 90Mhz clcock.
> > In design all lower level module are working above 100 Mhz, but in top
> > module after integarting sub blocks it works around 56 Mhz in
> > synthesis and working at 90Mhz on board.
> > so please tell me what is wrong with this design.
> > Regards
> > J.Ram
>
> What is wrong is your expectation that based on a sample of one board that
> works at 90 MHz, that all boards over all rated temperature conditions over
> all possible input conditions will also work at that speed.
>
> It's not at all unusual to expect that a single board in a lab environment
> might happen to work at ~50% over the speed computed by the timing analyzer.
> Try building thousands of such boards and put them in the extreme rated
> temperature conditions and give them the most stressful input pattern and
> see how many of those boards still work.  What you'll likely find is a lot
> of fallout...but again you might have a few survivors.
>
> KJ

KJ nailed it.

Andy

"J.Ram" wrote:
> I developed a design in which i need a master clock of 90Mhz, so
> during synthesis max. freq obtained is 56Mhz and  timing is met for
> global clock of 50Mhz, but timing are not met for 90Mhz.
> but design is working on board for 90Mhz clcock.
[...]
> so please tell me what is wrong with this design.

What is wrong is that you are running the part out of spec.
It might work fine on some particular chips at room temperature,
and fail on other chips or at elevated temperatures.

If you modify the design to meet timing, then it will work on
all chips over the rated temperature range.

We all agree that it would be irresponsible to release a design that
does not meet timing specifications, and that the successful operation
of one board at a higher frequency really has no significance.
But you might want to explore WHY your timing analysis claims that the
design fails at such a low frequency.
Where are the >18 ns between clock edges, responsible for the 56 MHz
limit? Maybe it's easy to fix.
Peter Alfke

On May 21, 1:30 pm, Eric Smith <e...@brouhaha.com> wrote:
> "J.Ram" wrote:
> > I developed a design in which i need a master clock of 90Mhz, so
> > during synthesis max. freq obtained is 56Mhz and  timing is met for
> > global clock of 50Mhz, but timing are not met for 90Mhz.
> > but design is working on board for 90Mhz clcock.
> [...]
> > so please tell me what is wrong with this design.
>
> What is wrong is that you are running the part out of spec.
> It might work fine on some particular chips at room temperature,
> and fail on other chips or at elevated temperatures.
>
> If you modify the design to meet timing, then it will work on
> all chips over the rated temperature range.