I need to write some timing constraints for an ProAsic device. The Designer tool doesn't seem to cater for what I need; as follows: FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) captures data on the clk falling edge (Same clock with very low skew to both devices) Similarly Actel outputs data on clk falling edge & Xilinx capture on rising edge. I have the Xilinx input & output delays and the clock period is 30 ns. The clock M/S ratio is 40/60 though, so the total allowed time from one device clocking out to the other device clocking in is therefore 12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. So how do I apply the constraints to my Actel chip; I've never used an SDC file, so some tips or pointers to examples would be useful. TIA, Niv
Actel timing constraints
Started by ●May 24, 2007
Reply by ●May 24, 20072007-05-24
Niv (KP) wrote:> I need to write some timing constraints for an ProAsic device. The > Designer tool doesn't seem to cater for what I need; as follows: > > FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) > captures data on the clk falling edge (Same clock with very low skew > to both devices) > Similarly Actel outputs data on clk falling edge & Xilinx capture on > rising edge. > I have the Xilinx input & output delays and the clock period is 30 ns. > The clock M/S ratio is 40/60 though, so the total allowed time from > one device clocking out to the other device clocking in is therefore > 12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. > > So how do I apply the constraints to my Actel chip; I've never used an > SDC file, so some tips or pointers to examples would be useful. > > TIA, Niv > >You need the "set_output_delay" constraint I think. Designer "help" menu will tell you how to use it. Alternatively use the Timing Analyser GUI in Designer to set the constraints. Alan
Reply by ●May 25, 20072007-05-25
On 24 May, 21:16, Alan Myler <amy...@eircom.net> wrote:> Niv (KP) wrote: > > I need to write some timing constraints for an ProAsic device. The > > Designer tool doesn't seem to cater for what I need; as follows: > > > FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) > > captures data on the clk falling edge (Same clock with very low skew > > to both devices) > > Similarly Actel outputs data on clk falling edge & Xilinx capture on > > rising edge. > > I have the Xilinx input & output delays and the clock period is 30 ns. > > The clock M/S ratio is 40/60 though, so the total allowed time from > > one device clocking out to the other device clocking in is therefore > > 12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. > > > So how do I apply the constraints to my Actel chip; I've never used an > > SDC file, so some tips or pointers to examples would be useful. > > > TIA, Niv > > You need the "set_output_delay" constraint I think. Designer "help" menu > will tell you how to use it. > > Alternatively use the Timing Analyser GUI in Designer to set the > constraints. > > Alan- Hide quoted text - > > - Show quoted text -I find the timing analyser GUI (or "Smartime") confusing. I know exactly what I want to say, but I just can't understand how to apply my requirements using the Actel GUI. I've even asked the Actel FAE and he couldn't tell me how to do it, so what chance do I have! I think a script is a far better method anyway, as it's fully repeatable without having to remember what boxes were/were not ticked etc. Niv.
Reply by ●May 25, 20072007-05-25
Niv (KP) wrote:> On 24 May, 21:16, Alan Myler <amy...@eircom.net> wrote: > >>Niv (KP) wrote: >> >>>I need to write some timing constraints for an ProAsic device. The >>>Designer tool doesn't seem to cater for what I need; as follows: >>> >>>FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) >>>captures data on the clk falling edge (Same clock with very low skew >>>to both devices) >>>Similarly Actel outputs data on clk falling edge & Xilinx capture on >>>rising edge. >>>I have the Xilinx input & output delays and the clock period is 30 ns. >>>The clock M/S ratio is 40/60 though, so the total allowed time from >>>one device clocking out to the other device clocking in is therefore >>>12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. >>> >>>So how do I apply the constraints to my Actel chip; I've never used an >>>SDC file, so some tips or pointers to examples would be useful. >>> >>>TIA, Niv >>> >>You need the "set_output_delay" constraint I think. Designer "help" menu >>will tell you how to use it. >> >>Alternatively use the Timing Analyser GUI in Designer to set the >>constraints. >> >>Alan- Hide quoted text - >> >>- Show quoted text - >> > > I find the timing analyser GUI (or "Smartime") confusing. I know > exactly what I want to say, but I just can't understand how to apply > my requirements using the Actel GUI. I've even asked the Actel FAE > and he couldn't tell me how to do it, so what chance do I have! > > I think a script is a far better method anyway, as it's fully > repeatable without having to remember what boxes were/were not ticked > etc. > > Niv. > >Hi Niv, I agree, the GUI is a little confusing, and yes scripts are better. However, as a learning exercise it's not wasted time to enter the requirements via the GUI and see what results you achieve. (Perhaps double check the results using back-annotated gate-level simulation, just to be sure that you're getting what you hope you've specified.) BTW you can export the GUI contraints to an SDC file from Designer File->Export->ConstraintFiles Best of luck. Alan
Reply by ●June 5, 20072007-06-05
On 25 May, 09:13, Alan Myler <amy...@eircom.net> wrote:> Niv (KP) wrote: > > On 24 May, 21:16, Alan Myler <amy...@eircom.net> wrote: > > >>Niv (KP) wrote: > > >>>I need to write some timing constraints for an ProAsic device. The > >>>Designer tool doesn't seem to cater for what I need; as follows: > > >>>FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) > >>>captures data on the clk falling edge (Same clock with very low skew > >>>to both devices) > >>>Similarly Actel outputs data on clk falling edge & Xilinx capture on > >>>rising edge. > >>>I have the Xilinx input & output delays and the clock period is 30 ns. > >>>The clock M/S ratio is 40/60 though, so the total allowed time from > >>>one device clocking out to the other device clocking in is therefore > >>>12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. > > >>>So how do I apply the constraints to my Actel chip; I've never used an > >>>SDC file, so some tips or pointers to examples would be useful. > > >>>TIA, Niv > > >>You need the "set_output_delay" constraint I think. Designer "help" menu > >>will tell you how to use it. > > >>Alternatively use the Timing Analyser GUI in Designer to set the > >>constraints. > > >>Alan- Hide quoted text - > > >>- Show quoted text - > > > I find the timing analyser GUI (or "Smartime") confusing. I know > > exactly what I want to say, but I just can't understand how to apply > > my requirements using the Actel GUI. I've even asked the Actel FAE > > and he couldn't tell me how to do it, so what chance do I have! > > > I think a script is a far better method anyway, as it's fully > > repeatable without having to remember what boxes were/were not ticked > > etc. > > > Niv. > > Hi Niv, > > I agree, the GUI is a little confusing, and yes scripts are better. > > However, as a learning exercise it's not wasted time to enter the > requirements via the GUI and see what results you achieve. (Perhaps > double check the results using back-annotated gate-level simulation, > just to be sure that you're getting what you hope you've specified.) > > BTW you can export the GUI contraints to an SDC file from Designer > File->Export->ConstraintFiles > > Best of luck. > > Alan- Hide quoted text - > > - Show quoted text -Played around with this a bit: If I set clock to output delay, which is comprehensible, as 7ns, the saved .sdc file translates this to 23 ns output delay, which is patently wrong for my application as the the time between falling edge (Actel o/p) and rising edge (Xlx i/p) is only 15ns (possibly only 12ns with 60/40 clock). So, do I amend this to say output delay = 5ns where the 5ns := 1ns track delay, plus the 4ns Xilinx input delay (i/ p pad to register i/p max path), and forget about the clock period? TIA, Kev P.
