accesing JTAG ports on GPIOs

Hi there,
I have a virtex II board (xc2v1000), unfortunately no jtag signals are
routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
from using ChipScope pro on this board to debug my design. Is it
possible somehow to tap the jtag ports internally and route them to
GPIOs which are available on th board! In that case, I will insert the
ChipScope Pro core in my design in the normal fashion and will put
that part of the code in the design that will tap the JTAG ports
internally and will map them to other GPIOs?


Farhan

maverick schrieb:
> Hi there,
> I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> from using ChipScope pro on this board to debug my design. Is it
> possible somehow to tap the jtag ports internally and route them to
> GPIOs which are available on th board! In that case, I will insert the
> ChipScope Pro core in my design in the normal fashion and will put
> that part of the code in the design that will tap the JTAG ports
> internally and will map them to other GPIOs?
>
>
> Farhan
sure, get it here:

http://code.google.com/p/fpga-tools/downloads/list

Antti

On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> maverick schrieb:> Hi there,
> > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > from using ChipScope pro on this board to debug my design. Is it
> > possible somehow to tap the jtag ports internally and route them to
> > GPIOs which are available on th board! In that case, I will insert the
> > ChipScope Pro core in my design in the normal fashion and will put
> > that part of the code in the design that will tap the JTAG ports
> > internally and will map them to other GPIOs?
>
> > Farhan
>
> sure, get it here:
>
> http://code.google.com/p/fpga-tools/downloads/list
>
> Antti

Hi Antti,
Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
file. Unfortunately, I am a Verilog writer and do not have much
exposure to VHDL code. What I have understood from the code is, I have
to instantiate this primitive into my design and map the IO to FPGA
IOs. It will make my life easy if you can demonstrate it by making
required changes in the following simple counter code as it is not
clear to me how would I make the chipscope logic communicate to this
primitive. In the following code, assume that I have to monitor 8-bit
counter reg in chipscope pro.

//----------------------------------------
module my_counter(clk,
                              rst,
                              led
                              );

input clk;
input rst;
output led;

reg [7:0] counter;

always @(posedge clk)
if(rst)
 counter <= #1 0;
else
 counter <= #1 counter + 1;

assign led = counter[7];

endmodule

//---------------------------------------------------

BTW, do you have the Verilog version of the same primitives?

Thanks and waiting for your help,
Farhan

On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
> On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:

>
> > maverick schrieb:> Hi there,
> > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > from using ChipScope pro on this board to debug my design. Is it
> > > possible somehow to tap the jtag ports internally and route them to
> > > GPIOs which are available on th board! In that case, I will insert the
> > > ChipScope Pro core in my design in the normal fashion and will put
> > > that part of the code in the design that will tap the JTAG ports
> > > internally and will map them to other GPIOs?
>
> > > Farhan
>
> > sure, get it here:
>
> >http://code.google.com/p/fpga-tools/downloads/list
>
> > Antti
>
> Hi Antti,
> Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> file. Unfortunately, I am a Verilog writer and do not have much
> exposure to VHDL code. What I have understood from the code is, I have
> to instantiate this primitive into my design and map the IO to FPGA
> IOs. It will make my life easy if you can demonstrate it by making
> required changes in the following simple counter code as it is not
> clear to me how would I make the chipscope logic communicate to this
> primitive. In the following code, assume that I have to monitor 8-bit
> counter reg in chipscope pro.
>

just use the VHDL in your verilog design should be no issue
all modern synthesis tools support mixed language designs.

Antti

On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
>
>
>
>
> > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > maverick schrieb:> Hi there,
> > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > from using ChipScope pro on this board to debug my design. Is it
> > > > possible somehow to tap the jtag ports internally and route them to
> > > > GPIOs which are available on th board! In that case, I will insert the
> > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > that part of the code in the design that will tap the JTAG ports
> > > > internally and will map them to other GPIOs?
>
> > > > Farhan
>
> > > sure, get it here:
>
> > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > Antti
>
> > Hi Antti,
> > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > file. Unfortunately, I am a Verilog writer and do not have much
> > exposure to VHDL code. What I have understood from the code is, I have
> > to instantiate this primitive into my design and map the IO to FPGA
> > IOs. It will make my life easy if you can demonstrate it by making
> > required changes in the following simple counter code as it is not
> > clear to me how would I make the chipscope logic communicate to this
> > primitive. In the following code, assume that I have to monitor 8-bit
> > counter reg in chipscope pro.
>
> just use the VHDL in your verilog design should be no issue
> all modern synthesis tools support mixed language designs.
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Thanks Antti for the reply,
Yes, I am aware of the feature of mixed language synthesis. But here,
I am more interested to know how to use these soft BSCAN primitives in
the case where I need to use Chip SCope pro as well. Kindly modify the
sample program I posted earlier to show the changes required to
incorporate BSCAN primitive to use chip scope pro using GPIOs.

Thanks

On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
> On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
>
>
> > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > maverick schrieb:> Hi there,
> > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > that part of the code in the design that will tap the JTAG ports
> > > > > internally and will map them to other GPIOs?
>
> > > > > Farhan
>
> > > > sure, get it here:
>
> > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > Antti
>
> > > Hi Antti,
> > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > file. Unfortunately, I am a Verilog writer and do not have much
> > > exposure to VHDL code. What I have understood from the code is, I have
> > > to instantiate this primitive into my design and map the IO to FPGA
> > > IOs. It will make my life easy if you can demonstrate it by making
> > > required changes in the following simple counter code as it is not
> > > clear to me how would I make the chipscope logic communicate to this
> > > primitive. In the following code, assume that I have to monitor 8-bit
> > > counter reg in chipscope pro.
>
> > just use the VHDL in your verilog design should be no issue
> > all modern synthesis tools support mixed language designs.
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -
>
> Thanks Antti for the reply,
> Yes, I am aware of the feature of mixed language synthesis. But here,
> I am more interested to know how to use these soft BSCAN primitives in
> the case where I need to use Chip SCope pro as well. Kindly modify the
> sample program I posted earlier to show the changes required to
> incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> Thanks- Hide quoted text -
>
> - Show quoted text -

Hi Antti,
I am anxiously waiting for your guidance on my problem. Kindly, do
reply....

Farhan

On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
> On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > maverick schrieb:> Hi there,
> > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > internally and will map them to other GPIOs?
>
> > > > > > Farhan
>
> > > > > sure, get it here:
>
> > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > Antti
>
> > > > Hi Antti,
> > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > required changes in the following simple counter code as it is not
> > > > clear to me how would I make the chipscope logic communicate to this
> > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > counter reg in chipscope pro.
>
> > > just use the VHDL in your verilog design should be no issue
> > > all modern synthesis tools support mixed language designs.
>
> > > Antti- Hide quoted text -
>
> > > - Show quoted text -
>
> > Thanks Antti for the reply,
> > Yes, I am aware of the feature of mixed language synthesis. But here,
> > I am more interested to know how to use these soft BSCAN primitives in
> > the case where I need to use Chip SCope pro as well. Kindly modify the
> > sample program I posted earlier to show the changes required to
> > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > Thanks- Hide quoted text -
>
> > - Show quoted text -
>
> Hi Antti,
> I am anxiously waiting for your guidance on my problem. Kindly, do
> reply....
>
> Farhan- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

Dear maverick,

sure I can: "Kindly modify the sample program you posted posted
earlier.."
so if you wish that please contact me in private  - the hourly fee is
50EUR + 19%TAX

if you just want other people to do your work, or things you dont want
to learn
then I guess you must wait, or seek another job

Antti

On Jun 1, 11:06 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
>
>
>
>
>
> > On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > maverick schrieb:> Hi there,
> > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > > internally and will map them to other GPIOs?
>
> > > > > > > Farhan
>
> > > > > > sure, get it here:
>
> > > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > > Antti
>
> > > > > Hi Antti,
> > > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > > required changes in the following simple counter code as it is not
> > > > > clear to me how would I make the chipscope logic communicate to this
> > > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > > counter reg in chipscope pro.
>
> > > > just use the VHDL in your verilog design should be no issue
> > > > all modern synthesis tools support mixed language designs.
>
> > > > Antti- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > Thanks Antti for the reply,
> > > Yes, I am aware of the feature of mixed language synthesis. But here,
> > > I am more interested to know how to use these soft BSCAN primitives in
> > > the case where I need to use Chip SCope pro as well. Kindly modify the
> > > sample program I posted earlier to show the changes required to
> > > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > > Thanks- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Antti,
> > I am anxiously waiting for your guidance on my problem. Kindly, do
> > reply....
>
> > Farhan- Zitierten Text ausblenden -
>
> > - Zitierten Text anzeigen -
>
> Dear maverick,
>
> sure I can: "Kindly modify the sample program you posted posted
> earlier.."
> so if you wish that please contact me in private  - the hourly fee is
> 50EUR + 19%TAX
>
> if you just want other people to do your work, or things you dont want
> to learn
> then I guess you must wait, or seek another job
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Hi Antti,
I never meant it that way that you do my work. , I am sorry in case if
I have made you feel like that. Anyways, thanks for your help.

On 1 Jun., 08:42, maverick <sheikh.m.far...@gmail.com> wrote:
> On Jun 1, 11:06 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
>
>
> > On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > > maverick schrieb:> Hi there,
> > > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > > > internally and will map them to other GPIOs?
>
> > > > > > > > Farhan
>
> > > > > > > sure, get it here:
>
> > > > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > > > Antti
>
> > > > > > Hi Antti,
> > > > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > > > required changes in the following simple counter code as it is not
> > > > > > clear to me how would I make the chipscope logic communicate to this
> > > > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > > > counter reg in chipscope pro.
>
> > > > > just use the VHDL in your verilog design should be no issue
> > > > > all modern synthesis tools support mixed language designs.
>
> > > > > Antti- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Thanks Antti for the reply,
> > > > Yes, I am aware of the feature of mixed language synthesis. But here,
> > > > I am more interested to know how to use these soft BSCAN primitives in
> > > > the case where I need to use Chip SCope pro as well. Kindly modify the
> > > > sample program I posted earlier to show the changes required to
> > > > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > > > Thanks- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > Hi Antti,
> > > I am anxiously waiting for your guidance on my problem. Kindly, do
> > > reply....
>
> > > Farhan- Zitierten Text ausblenden -
>
> > > - Zitierten Text anzeigen -
>
> > Dear maverick,
>
> > sure I can: "Kindly modify the sample program you posted posted
> > earlier.."
> > so if you wish that please contact me in private  - the hourly fee is
> > 50EUR + 19%TAX
>
> > if you just want other people to do your work, or things you dont want
> > to learn
> > then I guess you must wait, or seek another job
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -
>
> Hi Antti,
> I never meant it that way that you do my work. , I am sorry in case if
> I have made you feel like that. Anyways, thanks for your help.- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

well read what you wrote your self.
what you need can be done with a few mouseclicks.
but if I do it for you never learn.

Antti

On Jun 1, 11:44 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 08:42, maverick <sheikh.m.far...@gmail.com> wrote:
>
>
>
>
>
> > On Jun 1, 11:06 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > > > maverick schrieb:> Hi there,
> > > > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > > > > internally and will map them to other GPIOs?
>
> > > > > > > > > Farhan
>
> > > > > > > > sure, get it here:
>
> > > > > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > > > > Antti
>
> > > > > > > Hi Antti,
> > > > > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > > > > required changes in the following simple counter code as it is not
> > > > > > > clear to me how would I make the chipscope logic communicate to this
> > > > > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > > > > counter reg in chipscope pro.
>
> > > > > > just use the VHDL in your verilog design should be no issue
> > > > > > all modern synthesis tools support mixed language designs.
>
> > > > > > Antti- Hide quoted text -
>
> > > > > > - Show quoted text -
>
> > > > > Thanks Antti for the reply,
> > > > > Yes, I am aware of the feature of mixed language synthesis. But here,
> > > > > I am more interested to know how to use these soft BSCAN primitives in
> > > > > the case where I need to use Chip SCope pro as well. Kindly modify the
> > > > > sample program I posted earlier to show the changes required to
> > > > > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > > > > Thanks- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Hi Antti,
> > > > I am anxiously waiting for your guidance on my problem. Kindly, do
> > > > reply....
>
> > > > Farhan- Zitierten Text ausblenden -
>
> > > > - Zitierten Text anzeigen -
>
> > > Dear maverick,
>
> > > sure I can: "Kindly modify the sample program you posted posted
> > > earlier.."
> > > so if you wish that please contact me in private  - the hourly fee is
> > > 50EUR + 19%TAX
>
> > > if you just want other people to do your work, or things you dont want
> > > to learn
> > > then I guess you must wait, or seek another job
>
> > > Antti- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Antti,
> > I never meant it that way that you do my work. , I am sorry in case if
> > I have made you feel like that. Anyways, thanks for your help.- Zitierten Text ausblenden -
>
> > - Zitierten Text anzeigen -
>
> well read what you wrote your self.
> what you need can be done with a few mouseclicks.
> but if I do it for you never learn.
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Sure,
I will work on it,
thanks