Timing model for MultiTrack interconnects in Stratix?

Hi,

I am interested in the timing model of the MultiTrack interconnects on
Stratix.

The timing models for most resources (LEs, M4ks, IOs, etc) are
described in detail in the Stratix handbook, but, curiously, while the
symbols are defined for the MultiTracks (R4, R8, R24, C4, C8, C16) in
the latest handbook (pg 4-25), the actual timing numbers are never
given.

Does anyone have this information? I am digging into a DSP circuit
using Chip Editor and am very curious what the tPD's are for the
various MultiTracks used in the critical path (I know the overall tPD
from the timing analysis report).

-- Pete

Hi Peter,

The delay of the interconnect is both easy and complicated to give you.  The
quick answer is yes, we know the average delay of these resources (see
unofficial table below).  I'll enquire as to why we don't have delays or
delay ranges specified in the data sheet.

The long answer is that the delay of a given resource in Quartus will vary
due to a variety of reasons.
- # of active fanouts along the line (usually 1-2, but could be high
depending on route)
- # of inactive loads long the wire (doesn't vary too much)
- # of partially active loads -- these can happen when a two-stage mux has
multiple 1st stage inputs turned on due to sharing of configuration RAM
bits.
- Distance traveled.  If you travel only four units along an R24 wire, you
won't get the full RC delay due to resistive shielding of down-stream
capacitance.
- Edge rate of incoming signal.  This in turn is affected by the resource
used previously -- a R24 -> R4 could have different edge rate than R4 -> R4.
It will also be affected by that resource's loading.
- Blocks passed.  An R4 wire that passes over four LABs will be different in
length (physically) than an R4 that crosses an M4K block + three LABs.
Also, a C4 wire next to a clock spine may have slightly greater loading than
one between two LABs.
- Exact wire used.  Two different R4 wires that appear identical in all
these ways can have different timing due to what metal layer they are routed
on or due to physical proximity to other wires being different.
- Rising/falling transition.  Delay can vary depending on whether the input
is a rising or falling transition.

Quartus will give you the right answer to routing delay.  All these factors
do is make it a little more difficult to predict the precise delay you will
see in advance of timing analysis.  The allocation of delay to a particular
resource in a full routing path is somewhat arbitrary and depends on
measurement points and how we choose to bin the delay.

The following data was extracted from the critical paths of a large number
of typical user designs, and thus is representative of the types of paths
that tend to occur on the critical path.  It is not the maximum nor minimum
delay you will see on this type of resource.

Stratix -5 Routing Delays (Mux + Buffer + Wire):

R4           303 ps
R8           373 ps
R24          503 ps
C4           467 ps
C8           650 ps
C16          525 ps
LAB Line     463 ps
LE Output   231 ps
Local Line   353 ps

Regards,

Paul Leventis
Altera Corp.

Thanks, Paul, for the detailed answer. Very much appreciated.

If I understand the handbook correctly, each LAB can drive an R4 to
its left or right. But I haven't found out how many signals in total
can be driven on the various MultiTracks (ie. how wide are they?).

Also, does Altera have training courses that describe the architecture
to this level of detail? I understand most people are not concerned or
interested in it, so it may not be practical to have seminars on it.

-- Pete


"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<g3kRb.52563$iLV.46589@twister01.bloor.is.net.cable.rogers.com>...
> Hi Peter,
> 
> The delay of the interconnect is both easy and complicated to give you.  The
> quick answer is yes, we know the average delay of these resources (see
> unofficial table below).  I'll enquire as to why we don't have delays or
> delay ranges specified in the data sheet.
> 
> The long answer is that the delay of a given resource in Quartus will vary
> due to a variety of reasons.
> - # of active fanouts along the line (usually 1-2, but could be high
> depending on route)
> - # of inactive loads long the wire (doesn't vary too much)
> - # of partially active loads -- these can happen when a two-stage mux has
> multiple 1st stage inputs turned on due to sharing of configuration RAM
> bits.
> - Distance traveled.  If you travel only four units along an R24 wire, you
> won't get the full RC delay due to resistive shielding of down-stream
> capacitance.
> - Edge rate of incoming signal.  This in turn is affected by the resource
> used previously -- a R24 -> R4 could have different edge rate than R4 -> R4.
> It will also be affected by that resource's loading.
> - Blocks passed.  An R4 wire that passes over four LABs will be different in
> length (physically) than an R4 that crosses an M4K block + three LABs.
> Also, a C4 wire next to a clock spine may have slightly greater loading than
> one between two LABs.
> - Exact wire used.  Two different R4 wires that appear identical in all
> these ways can have different timing due to what metal layer they are routed
> on or due to physical proximity to other wires being different.
> - Rising/falling transition.  Delay can vary depending on whether the input
> is a rising or falling transition.
> 
> Quartus will give you the right answer to routing delay.  All these factors
> do is make it a little more difficult to predict the precise delay you will
> see in advance of timing analysis.  The allocation of delay to a particular
> resource in a full routing path is somewhat arbitrary and depends on
> measurement points and how we choose to bin the delay.
> 
> The following data was extracted from the critical paths of a large number
> of typical user designs, and thus is representative of the types of paths
> that tend to occur on the critical path.  It is not the maximum nor minimum
> delay you will see on this type of resource.
> 
> Stratix -5 Routing Delays (Mux + Buffer + Wire):
> 
> R4           303 ps
> R8           373 ps
> R24          503 ps
> C4           467 ps
> C8           650 ps
> C16          525 ps
> LAB Line     463 ps
> LE Output   231 ps
> Local Line   353 ps
> 
> Regards,
> 
> Paul Leventis
> Altera Corp.

Hi Peter,

> If I understand the handbook correctly, each LAB can drive an R4 to
> its left or right. But I haven't found out how many signals in total
> can be driven on the various MultiTracks (ie. how wide are they?).

The "cross-section" of the routing channel in Stratix is 160 R4 wires, 48 R8
wires, 80 C4 wires, 32 C8 wires, 24 R24 wires, and 16 R16 wires.

Each LE can drive C4/C8 wires in the channels to the left and right of the
LE, as well as R4/R8 wires that start "above and to the left" and "above and
to the right" of the LE.  Of course, this is all very fuzzy since this is a
logical, not a physical, representation of things.  But basically it means
that you can get from an LE to another LE that is up to four or eight LABs
away (not including the first one) in either direction in a single hop.  You
get onto the R24/C16 wires from R4 wires, and they can drive R24/C16/R4/C4
wires to eventually get to other blocks.  On top of this, there are paths
that take you from an LE output to the LAB line of adjacent labs, bypassing
the routing.

Things are little trickier near the DSP, M4K, and MRAM blocks.  For the DSP
and M4K blocks, basically pretend there are two LABs worth of routing that
are accessable by the DSP/M4K block, minus the vertical channel.

BTW, another way to see the routing that was used (rather than using Chip
Editor) is to back-annotate  your fitting, including the routing.  This will
produce a file named <design>.rcf in your project directory that contains
the routing.

You can also create your own routing constraints, with wild-carding, by
editing the RCF file.  See the QUIP documentation
(http://www.altera.com/education/univ/quip/quip-overview.html) for more
information on the RCF file format.

> Also, does Altera have training courses that describe the architecture
> to this level of detail? I understand most people are not concerned or
> interested in it, so it may not be practical to have seminars on it.

Looking at our web site, "Fundamental Design Techniques for Stratix Devices"
looks like it could cover this material, but probably not in too much more
detail.  I'd contact Altera Customer Training (custrain@altera.com) for help
in determining if an appropriate training session exists.

My guess is that knowing the routing architecture to this level of detail
isn't too handy to the typical end user.  The router is quite good at
optimizing things, though it is good to know how far you can go before you
must add additional routing hops, especially when floorplanning a design
manually via LogicLock.

I believe that there is a way in the Timing Closure floorplan view to see a
histogram of the delays from a source LE to destination LEs -- it tells you
where you can reach in what amount of delay.  But I don't recall how to get
to this feature as I don't actually get to use Quartus too much myself.
Looking at this view can give you a good intuition on the directional bias
(speed-wise) of the routing architecture as well as where things should be
placed relative to one another for maximum speed.

Regards,

Paul Leventis
Altera Corp.