How to deal with unavoidable setup time violation in CoolRunner II cpld?

Hi,
I apologize if this question is too stupid... basically I want to
build a protocol analyzer with a CoolRunner II cpld. the CPLD will
watch the bus line and extract data. I have passed behaviorial
simulation and fitted the device. but post-fit timing simulation gives
me some setup time violations and the output goes to X afterwards. I
read document that says ASYNC_REG can be used but it is not  available
on coolrunner cpld. Then I'm very concerned about what happens in the
real circuit. The bus line will not switch in sync with the sampling
clock, due to different clock domains, jitters etc. what happens in
the real circuit when the setup time is violated? will the cpld go
into metastable state for ever? This must be an old problem that has
been long solved, but how? can anyone help? thanks a lot....

Hsu

On 6 22 ,   10 28 , cxu...@yahoo.com wrote:
> Hi,
> I apologize if this question is too stupid... basically I want to
> build a protocol analyzer with a CoolRunner II cpld. the CPLD will
> watch the bus line and extract data. I have passed behaviorial
> simulation and fitted the device. but post-fit timing simulation gives
> me some setup time violations and the output goes to X afterwards. I
> read document that says ASYNC_REG can be used but it is not  available
> on coolrunner cpld. Then I'm very concerned about what happens in the
> real circuit. The bus line will not switch in sync with the sampling
> clock, due to different clock domains, jitters etc. what happens in
> the real circuit when the setup time is violated? will the cpld go
> into metastable state for ever? This must be an old problem that has
> been long solved, but how? can anyone help? thanks a lot....
>
> Hsu

Just want to add that I have a local oversampling clock, and the bus
could switch at anytime, say 0.1ns before the clock edge. and the cpld
requires setup time of 1.8ns.

 cxu_dl@yahoo.com wrote:

> On 6 22 ,   10 28 , cxu...@yahoo.com wrote:
>> Hi,
>> I apologize if this question is too stupid... basically I want to
>> build a protocol analyzer with a CoolRunner II cpld. the CPLD will
>> watch the bus line and extract data. I have passed behaviorial
>> simulation and fitted the device. but post-fit timing simulation gives
>> me some setup time violations and the output goes to X afterwards. I
>> read document that says ASYNC_REG can be used but it is not  available
>> on coolrunner cpld. Then I'm very concerned about what happens in the
>> real circuit. The bus line will not switch in sync with the sampling
>> clock, due to different clock domains, jitters etc. what happens in
>> the real circuit when the setup time is violated? will the cpld go
>> into metastable state for ever? This must be an old problem that has
>> been long solved, but how? can anyone help? thanks a lot....
>>
>> Hsu
> 
> Just want to add that I have a local oversampling clock, and the bus
> could switch at anytime, say 0.1ns before the clock edge. and the cpld
> requires setup time of 1.8ns.

You can't get rid of metastability, but you can reduce it to
spectacularly low likelihoods.

The classic way of doing this is to route the signals through
extra flip-flops. 1-2 are usually enough for most applications.

Violating the setup time on the first FF gives you a certain
chance of it entering a metastable state. It won't stay in it
forever - it just takes longer to switch. The metastable state
must last longer than the clock period to affect the second FF,
which is very unlikely.

The critical setup time windows which could cause a problem are in
the sub-femtosecond range - somewhere within your setup time window.
I think Xilinx have a appnote somewhere about the details.

Kind regards,

Iwo

If the setup time on the FF is not met, then it could possibly enter
the metastable state.  If it does, it will recover rather quickly...I
can't remember the exact figure...but you can't be certain of any
output.  It could go either way.  Even if it doesn't go metastable,
once you break the setup time, you cannot know for certain what the
output will be.  Therefore, you would never be able to 100% trust your
bus analyzer.  I am basing this on how I understand you post.

You mention in the second one that you are using a 'local oversampling
clock'.  Is this just some integer multiple of the bus speed?  If it
is, then you can try to figure out a way to do data recovery on the
oversampled data.  Then you can shove data into the CPLD
asynchronously, oversample it X times, recover the data, push it into
the local clock domain, and analyze it.

cxu_dl@yahoo.com wrote:

> Just want to add that I have a local oversampling clock, and the bus
> could switch at anytime, say 0.1ns before the clock edge. and the cpld
> requires setup time of 1.8ns.
> 

Setup violations are unavoidable in synchronizers.
I would use two flop synchronizers in a separate
entity/module and just assume that it works.
The alternative is to use false path constraints for STA.

Make sure the fast clock period is less
than the input pulse widths, and use the
slow clock only as in input.

      -- Mike Treseler

The problem with violating set-up time is not the ambiguity of the
output. If the input switches withing that window, then a 0 as an
answer is every bit as good as a 1. Who cares?
The real problem is the increased output delay,if the input changes
during that sub-femtosecond critial part of the set-up time window.
Then the output may fall back at an undefined time after its last
clock.
But modern flip-flops are very fast. A metastable delay of more than 3
ns is extremely rare.
The Xilinx app note is XAPP094 (I think)
You can also google: Metastability, Xilinx, Alfke...
Peter Alfke


On Jun 22, 8:57 am, Iwo Mergler <Iwo.Merg...@soton.sc.philips.com>
wrote:
>  cxu...@yahoo.com wrote:
> > On 6 22 ,   10 28 , cxu...@yahoo.com wrote:
> >> Hi,
> >> I apologize if this question is too stupid... basically I want to
> >> build a protocol analyzer with a CoolRunner II cpld. the CPLD will
> >> watch the bus line and extract data. I have passed behaviorial
> >> simulation and fitted the device. but post-fit timing simulation gives
> >> me some setup time violations and the output goes to X afterwards. I
> >> read document that says ASYNC_REG can be used but it is not  available
> >> on coolrunner cpld. Then I'm very concerned about what happens in the
> >> real circuit. The bus line will not switch in sync with the sampling
> >> clock, due to different clock domains, jitters etc. what happens in
> >> the real circuit when the setup time is violated? will the cpld go
> >> into metastable state for ever? This must be an old problem that has
> >> been long solved, but how? can anyone help? thanks a lot....
>
> >> Hsu
>
> > Just want to add that I have a local oversampling clock, and the bus
> > could switch at anytime, say 0.1ns before the clock edge. and the cpld
> > requires setup time of 1.8ns.
>
> You can't get rid of metastability, but you can reduce it to
> spectacularly low likelihoods.
>
> The classic way of doing this is to route the signals through
> extra flip-flops. 1-2 are usually enough for most applications.
>
> Violating the setup time on the first FF gives you a certain
> chance of it entering a metastable state. It won't stay in it
> forever - it just takes longer to switch. The metastable state
> must last longer than the clock period to affect the second FF,
> which is very unlikely.
>
> The critical setup time windows which could cause a problem are in
> the sub-femtosecond range - somewhere within your setup time window.
> I think Xilinx have a appnote somewhere about the details.
>
> Kind regards,
>
> Iwo

On 6 23 ,   12 33 , motty <mottobla...@yahoo.com> wrote:
> If the setup time on the FF is not met, then it could possibly enter
> the metastable state.  If it does, it will recover rather quickly...I
> can't remember the exact figure...but you can't be certain of any
> output.  It could go either way.  Even if it doesn't go metastable,
> once you break the setup time, you cannot know for certain what the
> output will be.  Therefore, you would never be able to 100% trust your
> bus analyzer.  I am basing this on how I understand you post.
>
> You mention in the second one that you are using a 'local oversampling
> clock'.  Is this just some integer multiple of the bus speed?  If it
> is, then you can try to figure out a way to do data recovery on the
> oversampled data.  Then you can shove data into the CPLD
> asynchronously, oversample it X times, recover the data, push it into
> the local clock domain, and analyze it.

Thank you for the suggestion. yes the local clock is  a integer
multiple of the norminal bus speed. If the consequence of the timing
violation is a misinterpretation of 0 or 1 then it's not a problem ,
since it will be treated as bit width variation. My original concern
was that the output going into metable state and oscillate for
prolonged time. Now I read Peter's XAPP094 I no longer worry about
this, since my clock period is 20ns, way longer than the already
unlikely 3ns...

On 6 23 ,   1 02 , Peter Alfke <p...@xilinx.com> wrote:
> The problem with violating set-up time is not the ambiguity of the
> output. If the input switches withing that window, then a 0 as an
> answer is every bit as good as a 1. Who cares?
> The real problem is the increased output delay,if the input changes
> during that sub-femtosecond critial part of the set-up time window.
> Then the output may fall back at an undefined time after its last
> clock.
> But modern flip-flops are very fast. A metastable delay of more than 3
> ns is extremely rare.
> The Xilinx app note is XAPP094 (I think)
> You can also google: Metastability, Xilinx, Alfke...
> Peter Alfke
>
> On Jun 22, 8:57 am, Iwo Mergler <Iwo.Merg...@soton.sc.philips.com>
> wrote:
>
> >  cxu...@yahoo.com wrote:
> > > On 6 22 ,   10 28 , cxu...@yahoo.com wrote:
> > >> Hi,
> > >> I apologize if this question is too stupid... basically I want to
> > >> build a protocol analyzer with a CoolRunner II cpld. the CPLD will
> > >> watch the bus line and extract data. I have passed behaviorial
> > >> simulation and fitted the device. but post-fit timing simulation gives
> > >> me some setup time violations and the output goes to X afterwards. I
> > >> read document that says ASYNC_REG can be used but it is not  available
> > >> on coolrunner cpld. Then I'm very concerned about what happens in the
> > >> real circuit. The bus line will not switch in sync with the sampling
> > >> clock, due to different clock domains, jitters etc. what happens in
> > >> the real circuit when the setup time is violated? will the cpld go
> > >> into metastable state for ever? This must be an old problem that has
> > >> been long solved, but how? can anyone help? thanks a lot....
>
> > >> Hsu
>
> > > Just want to add that I have a local oversampling clock, and the bus
> > > could switch at anytime, say 0.1ns before the clock edge. and the cpld
> > > requires setup time of 1.8ns.
>
> > You can't get rid of metastability, but you can reduce it to
> > spectacularly low likelihoods.
>
> > The classic way of doing this is to route the signals through
> > extra flip-flops. 1-2 are usually enough for most applications.
>
> > Violating the setup time on the first FF gives you a certain
> > chance of it entering a metastable state. It won't stay in it
> > forever - it just takes longer to switch. The metastable state
> > must last longer than the clock period to affect the second FF,
> > which is very unlikely.
>
> > The critical setup time windows which could cause a problem are in
> > the sub-femtosecond range - somewhere within your setup time window.
> > I think Xilinx have a appnote somewhere about the details.
>
> > Kind regards,
>
> > Iwo

Thank you all for the kind suggestions and help, I added two flip-
flops synchronizers in front of my other logic to make it more
solid...
That APP NOTE was about Virtex II FPGA, I suppose flip-flops in
CoolRunner are the same, or even better than that, right?