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Confused about FPGA devices recommended by Xilinx for my FFT project

Started by Telenochek June 26, 2007
Hi everyone.

I have selected spartan 3E family for an FFT project due to its low
cost.
The FFT core (v 4.0) specs say that for spartan3E devices, the
footprint is as follows (see table)
and they "recommend" the device in the table.

FFT =EF=BB=BFLength  	         Slices     Block RAMs 	 18x18 Mults 	 	Device
---------------------------------------------------------------------------=
--------------------------------
256 	                       485 	      2 	          2
xc3s500e
1024 	                      517 	     3 	                 2
	           xc3s1200e
8192 	                      578 	    18                  2
	                  xc3s1600e
---------------------------------------------------------------------------=
---------------------------------

However, based on device datasheets, the devices recommended are way
overkill.
For example, lets take FFT length of 8192.

We need 578 slices, 18 BRAM, 2 mults.
Lets look at the family Spartan 3E:

Device   System Gates  Slices  BRAM     18x18mult
---------------------------------------------------------------------------=
---
XC3S100E 100K             960	  72kbit         4
---------------------------------------------------------------------------=
---

So according to this table, even the smallest device in the family
will be able to fit the FFT 8192 design.
Based on my experience, that's not going to happen, but the tables say
it will.

Can anyone explain why xilinx recommends a 1.6Mgate device for the FFT
of 8192 points,
whereas according to slices utilized it should fit into a 100kgate
device?

Thank you,
Best regards,
Telenochek

Hi Telenochek,
acording to the numbers you gave the advice from Xilinx was correct.
In your case it's not the number of LUTs that defines the border, but 
the BRAMS.

You need 18 BRAMs, each has a size of 18KBit in S3E devices.
Datasheet Page 4 says:
• Block RAM provides data storage in the form of
18-Kbit dual-port blocks.

so 18 x 18 x 1024 = 331776 Bits

and so the closest fitting device is the S3E500 with 360 KBits.


And that's what is said in the 4.1 Datasheet table 28 and 30.
In table 24 and 26 you find the s3E1600 Device, but the cores listed in 
there need more BRAMS, and Multiplyers, so they don't fit in the S3E500 
anymore. also, there are max Clock frequencies given in these tables. 
Maybe these can't be acheived with the smaller devices due to mapping or 
routing problems.

But anyway, if you are still unsure about the device you should choose 
just make a test-synthesis and implementation. If there's something 
wrong with the size of the chosen device you will know instantly, after 
the error messages and warnings are printed out. Takes just a few minutes.

Have a nice synthesis

    Eilert


Telenochek schrieb:
> Hi everyone. > > I have selected spartan 3E family for an FFT project due to its low > cost. > The FFT core (v 4.0) specs say that for spartan3E devices, the > footprint is as follows (see table) > and they "recommend" the device in the table. > > FFT Length Slices Block RAMs 18x18 Mults Device > ----------------------------------------------------------------------------------------------------------- > 256 485 2 2 > xc3s500e > 1024 517 3 2 > xc3s1200e > 8192 578 18 2 > xc3s1600e > ------------------------------------------------------------------------------------------------------------ > > However, based on device datasheets, the devices recommended are way > overkill. > For example, lets take FFT length of 8192. > > We need 578 slices, 18 BRAM, 2 mults. > Lets look at the family Spartan 3E: > > Device System Gates Slices BRAM 18x18mult > ------------------------------------------------------------------------------ > XC3S100E 100K 960 72kbit 4 > ------------------------------------------------------------------------------ > > So according to this table, even the smallest device in the family > will be able to fit the FFT 8192 design. > Based on my experience, that's not going to happen, but the tables say > it will. > > Can anyone explain why xilinx recommends a 1.6Mgate device for the FFT > of 8192 points, > whereas according to slices utilized it should fit into a 100kgate > device? > > Thank you, > Best regards, > Telenochek >
On Jun 25, 10:59 pm, backhus <n...@nirgends.xyz> wrote:
> Hi Telenochek, > acording to the numbers you gave the advice from Xilinx was correct. > In your case it's not the number of LUTs that defines the border, but > the BRAMS. > > You need 18 BRAMs, each has a size of 18KBit in S3E devices. > Datasheet Page 4 says: > =E2=80=A2 Block RAM provides data storage in the form of > 18-Kbit dual-port blocks. > > so 18 x 18 x 1024 =3D 331776 Bits > > and so the closest fitting device is the S3E500 with 360 KBits. > > And that's what is said in the 4.1 Datasheet table 28 and 30. > In table 24 and 26 you find the s3E1600 Device, but the cores listed in > there need more BRAMS, and Multiplyers, so they don't fit in the S3E500 > anymore. also, there are max Clock frequencies given in these tables. > Maybe these can't be acheived with the smaller devices due to mapping or > routing problems. > > But anyway, if you are still unsure about the device you should choose > just make a test-synthesis and implementation. If there's something > wrong with the size of the chosen device you will know instantly, after > the error messages and warnings are printed out. Takes just a few minutes. > > Have a nice synthesis > > Eilert > > Telenochek schrieb: > > > Hi everyone. > > > I have selected spartan 3E family for an FFT project due to its low > > cost. > > The FFT core (v 4.0) specs say that for spartan3E devices, the > > footprint is as follows (see table) > > and they "recommend" the device in the table. > > > FFT =EF=BB=BFLength Slices Block RAMs 18x18 Mults =
Device
> > -----------------------------------------------------------------------=
------------------------------------
> > 256 485 2 2 > > xc3s500e > > 1024 517 3 2 > > xc3s1200e > > 8192 578 18 2 > > xc3s1600e > > -----------------------------------------------------------------------=
-------------------------------------
> > > However, based on device datasheets, the devices recommended are way > > overkill. > > For example, lets take FFT length of 8192. > > > We need 578 slices, 18 BRAM, 2 mults. > > Lets look at the family Spartan 3E: > > > Device System Gates Slices BRAM 18x18mult > > -----------------------------------------------------------------------=
-------
> > XC3S100E 100K 960 72kbit 4 > > -----------------------------------------------------------------------=
------- Thanks!
> > > So according to this table, even the smallest device in the family > > will be able to fit the FFT 8192 design. > > Based on my experience, that's not going to happen, but the tables say > > it will. > > > Can anyone explain why xilinx recommends a 1.6Mgate device for the FFT > > of 8192 points, > > whereas according to slices utilized it should fit into a 100kgate > > device? > > > Thank you, > > Best regards, > > Telenochek