Xilinx FPGA to interface to special I/O

I have a specific application where the FPGA needs to generate SPI bus like interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at relatively slow speed of about 20MHz. The FPGA will drive out serial data out and serial clock out to the target device using lvcmos25 pudhpull driver and will be receiving serial data in.

The problem is that the traget device will have its vcc at 1.2V and and its Vee at -1.3V. As per my understanding FPGA can not drive out a waveform with 1.2v to -1.3V swing. How to do the voltage translatin without affecting the signal integrity?

Any help will be greatly appreciated.

Albert.

Albert Nguyen wrote:
> I have a specific application where the FPGA needs to generate SPI bus like interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at relatively slow speed of about 20MHz. The FPGA will drive out serial data out and serial clock out to the target device using lvcmos25 pudhpull driver and will be receiving serial data in.
> 
> The problem is that the traget device will have its vcc at 1.2V and and its Vee at -1.3V. As per my understanding FPGA can not drive out a waveform with 1.2v to -1.3V swing. How to do the voltage translatin without affecting the signal integrity?
> 
> Any help will be greatly appreciated.
> 
> Albert.

Wow, that is one strange setup.
What exists now, are Dual Vcc translators, but with your setup,
probably the best device is something like
this 90MBd isolator from ADI & -1.3V of gnd skew
is nothing to this device :)

http://www.analog.com/en/prod/0,2877,ADuM1401,00.html

-jg

Albert Nguyen wrote:
> I have a specific application where the FPGA needs to generate SPI bus like interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at relatively slow speed of about 20MHz. The FPGA will drive out serial data out and serial clock out to the target device using lvcmos25 pudhpull driver and will be receiving serial data in.
> 
> The problem is that the traget device will have its vcc at 1.2V and and its Vee at -1.3V. As per my understanding FPGA can not drive out a waveform with 1.2v to -1.3V swing. How to do the voltage translatin without affecting the signal integrity?
> 
> Any help will be greatly appreciated.
> 
> Albert.

Often this kind of setup can be achieved by simply shifting your 
reference.  If the "internal" circuitry can be changes to a 2.5V supply 
between -1.2V and +1.3V with no other ground-based reference, it's just 
a mental shift to get the right logic levels to/from the same places. 
If you have an external interface that's ground referenced in addition 
to your "split" supply, the technique won't work and level shifters will 
be needed.

Can you get by without ground-referenced I/O?

On 2007-06-28, Albert Nguyen <> wrote:
> I have a specific application where the FPGA needs to generate SPI
>
> The problem is that the traget device will have its vcc at 1.2V and and its Vee at -1.3V.

All SPI signals are unidirectional, so you should be able to level shift
with a few transistors.  Why not:

                 Vcc
                  +
                  |
                  |
          1k_   |<
 [SCK>---|___|--|
                |\     |
                  o-------.
                 .-.      |
                 | |   | ---
              500| |     --- 10p "load"
                 '-'   |  |
                  o-------'
                  |    |
                 ===
                 Vee


SCK high is > 1.2V, SCK low < 1.2V.  Be sure to park SCK low, and invert
the signals...

(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

John,

Thanks for you input. I looked at the ADUM1401 datasheet. So you are suggesting that on the FPGA side of this device, I connect the Vdd1 to 2.5 and Gnd1 to ground but on the other side of this device I connect the Vdd2 to +1.2 and GND2 to -1.3V. Is that correct?

Albert

Ben,

I am not able to see your picture clearly. I think that simple bipolar npn transistor can work if the biasing is done right. I am bit concerned about the rise time if the biaising is not done right.

Thanks.

Albert

John H,

The traget device will be running its VCC at 1.2V and Ground at -1.3V. Normally it will be running at 2.5 and 0 but in my application I need to run at +1.2V and -1.3V in order to comply with the differential electrical specification. But in doing so, the sideband control pins (SPI Bus pins) electrical changes.

You asked if I can get by without ground reference I/O. Are you suggesting to connect the FPGA outputs SCLK and SERIAL DATA IN, directly to the target device?

If it is just a matter of scope probing then I can get by without ground reference i/o.

Thanks.

Albert

Albert Nguyen wrote:
> John,
> 
> Thanks for you input. I looked at the ADUM1401 datasheet. So you are suggesting that on the FPGA side of this device, I connect the Vdd1 to 2.5 and Gnd1 to ground but on the other side of this device I connect the Vdd2 to +1.2 and GND2 to -1.3V. Is that correct?
> 
> Albert

Absolutely NOT my suggestion.

You want the FPGA to interface to those odd voltages.  Hook the FPGA 
Vcco to +1.2V and the FPGA GND signals all to -1.3V.  Just perform a 
mental shift of all FPGA voltaqes by 1.3V *IF* there are no other I/O 
that must interface as system ground referenced signals.  If you can 
make *all* I/O a 2.5V swing relative to -1.3V, everything can flow.

If you have TTL signals going in one side from an external source and 
the +1.2/-1.3V signalling on the other side, you will need external 
signal translation.  If your system is fully contained, there is no 
explicit need to make the ground reference for pushbutton-driven logic 
and the ground reference for the funky I/O levels of your unusual device 
the same potential.

All I'm suggesting is a mental shift of what "ground" is for an entire 
device.  But only if it can be applicable to the entire device.

Having FPGA VCC on 1.2V and GND on -1.3V is not possible as it affects many other FPGA signals.

Thanks.

Albert

<Albert Nguyen> wrote in message news:eea7b1c.7@webx.sUN8CHnE...
> Having FPGA VCC on 1.2V and GND on -1.3V is not possible as it affects 
> many other FPGA signals.
>
> Thanks.
>
> Albert

Then you absolutely need level translators.

I feel I lost you on the idea of shifting your rails to a different absolute 
voltage while keeping all the rails and signals properly specified relative 
to each other.  It may be your system doesn't need the absolute voltages 
you're planning.  Since I don't know enough about your system to see if a 
compromise can be made, just design level translators.

You might look at using PNP transistors with a pull-down to -1.3V to provide 
the +1.2V to -1.3V swing.