Forums

Analogue like signal interaction within cpld possible ????

Started by Ulrich Bangert June 28, 2007
Gents,

please allow me to confront you with some strange timing behaviour which I
have measured with an Xilinx  XC95108 cpld.

Consider two well conditioned clock signals of 10 MHz (both having EXACTLY
the same frequency) entering the cpld. Inside the cpld each clock signal is
divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz signals
enter an exclusive-or-gate which delivers an output signal where the
pulse/pause-relationship directly depends on the phase relationship of the
two input clocks.

If some of you feel reminded to something that you have seen before: Yes,
basically this is the principle of an so called linear phase comparator
which has been used to compare high stability clocks (for example cesium
clocks) against each other before high resolution time interval counters
like the HP5370 or the Stanford Research SR620 were available.

Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is a
bit beyond the discussion HOW this is achieved but you may believe me that
this is possible and that THIS is not part of the discussed problem. Now the
phase relationship of the clocks changes slowly in time as does the
pulse/pause relationship behind the xor gate. The pulse/pause relationship
of the xor's output can be measured by two completely different methods:

a) by generating an dc voltage which is directly proportional to the
pulse/pause relationship (again a bit tricky if you want it to be an really
high resolution measurement, but it  can  be done)

b) by directly measuring the output pulse width with an high resolution time
interval counter like the SR620 having a 25 ps single shot resolution for
time interval measurements.

It is important to note that both methods to measure can be applied at the
same time and that both methods (although based on completely different
physical laws) deliver results that despite some statistical fluctuations
are basically the same. That is why I am pretty sure that what I measure is
really an property of the signal itself and not one of the measurement
apparatus.

If I record the pulse width over time using the two methods and display it
graphically it looks like an pretty linear relationship at the first glance.
If however some math is applied to make it evident how good the linear
relationship really is met then the result is that there are fluctuations in
the pulse width in the order of some +/-450 ps from the expected values.

About these fluctuations the following facts are known:

1) They are not existent in the inputs clocks

2) Expressed in time units as well as expressed as an dc voltage the
fluctuations are orders of magnitude bigger than the resolution and
precision of the time/dc measurement.

3) The fluctuations are by no means of stochastical nature. Instead, If an
positive fluctuation is noticed at an certain phase between the clock
signals, an fluctuation of the same magnitude and sign  will be noticed  the
next time when the clock signals have the same phase relationship. Or in
other words: The pulse width is an direct function of the phase relationship
of the clocks + an error function which is an direct function of the phase
relationship between the clocks.

It seems as if the phase state of one of the signals can have an linear like
modulating effect on the phase state of the second signal (and perhaps vice
versa). Some of you may come to the conclusion that +/-450 ps is not an
number to cause real world troubles but in my case: The whole arrangement
has the intention to measure phase fluctuations of the input clocks that ARE
REALLY THERE but that are smaller at least one order of magnitude than the
noticed errors. And that is why +/-450 ps is an real annoying number for me.

Any hint will be highly appreciated
TIA, Ulrich Bangert




Ulrich Bangert wrote:
> Gents, > > please allow me to confront you with some strange timing behaviour which I > have measured with an Xilinx XC95108 cpld. > > Consider two well conditioned clock signals of 10 MHz (both having EXACTLY > the same frequency) entering the cpld. Inside the cpld each clock signal is > divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz signals > enter an exclusive-or-gate which delivers an output signal where the > pulse/pause-relationship directly depends on the phase relationship of the > two input clocks. > > If some of you feel reminded to something that you have seen before: Yes, > basically this is the principle of an so called linear phase comparator > which has been used to compare high stability clocks (for example cesium > clocks) against each other before high resolution time interval counters > like the HP5370 or the Stanford Research SR620 were available. > > Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is a > bit beyond the discussion HOW this is achieved but you may believe me that > this is possible and that THIS is not part of the discussed problem. Now the > phase relationship of the clocks changes slowly in time as does the > pulse/pause relationship behind the xor gate. The pulse/pause relationship > of the xor's output can be measured by two completely different methods: > > a) by generating an dc voltage which is directly proportional to the > pulse/pause relationship (again a bit tricky if you want it to be an really > high resolution measurement, but it can be done) > > b) by directly measuring the output pulse width with an high resolution time > interval counter like the SR620 having a 25 ps single shot resolution for > time interval measurements. > > It is important to note that both methods to measure can be applied at the > same time and that both methods (although based on completely different > physical laws) deliver results that despite some statistical fluctuations > are basically the same. That is why I am pretty sure that what I measure is > really an property of the signal itself and not one of the measurement > apparatus. > > If I record the pulse width over time using the two methods and display it > graphically it looks like an pretty linear relationship at the first glance. > If however some math is applied to make it evident how good the linear > relationship really is met then the result is that there are fluctuations in > the pulse width in the order of some +/-450 ps from the expected values. > > About these fluctuations the following facts are known: > > 1) They are not existent in the inputs clocks > > 2) Expressed in time units as well as expressed as an dc voltage the > fluctuations are orders of magnitude bigger than the resolution and > precision of the time/dc measurement. > > 3) The fluctuations are by no means of stochastical nature. Instead, If an > positive fluctuation is noticed at an certain phase between the clock > signals, an fluctuation of the same magnitude and sign will be noticed the > next time when the clock signals have the same phase relationship. Or in > other words: The pulse width is an direct function of the phase relationship > of the clocks + an error function which is an direct function of the phase > relationship between the clocks.
How often do you see this, 4 or 8 times per 2.5MHz cycle ?
> > It seems as if the phase state of one of the signals can have an linear like > modulating effect on the phase state of the second signal (and perhaps vice > versa). Some of you may come to the conclusion that +/-450 ps is not an > number to cause real world troubles but in my case: The whole arrangement > has the intention to measure phase fluctuations of the input clocks that ARE > REALLY THERE but that are smaller at least one order of magnitude than the > noticed errors. And that is why +/-450 ps is an real annoying number for me. > > Any hint will be highly appreciated > TIA, Ulrich Bangert
I think I have followed this. If you are trying to 'zoom into' the phase to high precisons, using analog Phase integration, there are some rules to follow. Vcc and Gnd must be VERY clean. That means no other clocks, and /4 is going to cause more edges and bounce, plus Vdd impedance noise is usually quite bad on CPLDs. Any edge that is very close to another, WILL move the threshold, and so cause phase non-linearities. Normally, these are so small, well under Tpd, so in the digital domain they do not matter much. [Some CPLDs will show Tpd delta, vs outputs loded ] This stuff is NOT on the chip designer's radar :) So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, preferable with Schmitt. eg LVC1G97, with analog Supply decoupling. You may even find, you cannot have both non-locked frequencies in the same package, so may need separate /4 blocks Also XOR gates will be quite good at 90' output, but will not be linear at needle pulse phase outputs, so if you need 360' phase with linearity, I would suggest look at dual quadrature XOR phase comparisons. (so one is in mid scale, when the other hits the edges) ( or even more phases, 4 would be simple from 10MHz, and use 4 ADC channels - then 3 of the 4 would be low-error ) -jg
Jim,

thanks for your remarks! Because I did not want to make it too difficult I
simplified my explanation a bit and left out some things that I regarded not
significant for the problem: It is NOT the cpld's xor output directly that I
am trying to integrate, which would be really very difficult with the
intended precision.

Instead this output merely drives an precision high speed diode based switch
built from some HSMS-2812 which connects an summing rc-element alternating
with two reference voltages that are indeed of highest quality in terms of
precicion, tempco and 'clean-ness' and yes, low impedance. While this
analogue circuitry has been suspected to be the source of problems it has
now (where the direct comparison with the TIC based measurments was
possible) turned out to work like charming.

> So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, > preferable with Schmitt. eg LVC1G97, with analog Supply decoupling.
Using an external xor will be the next thing that I am going to try. However, even this external xor will only drive the switch described above and therefore its supply will be less critical than you suggest. Because I am out for speed (10 MHz may not be the highest frequencies to compare) I ordered some 74AHC1G86 from Farnell. Do you think that the LVC part could be the better performer due to the Schmitt trigger?
> You may even find, you cannot have both non-locked frequencies in the > same package, so may need separate /4 blocks
This will be the next-next thing to do. Again I simplified a bit: The divide by 4 flip-flops are the things that provide symmetrical quadrature outputs. In front of them are programmable predividers that enable the circuit to compare two signals of not the same frequency. However for the experiment described these predividers were de-activated. These predividers are the reason for using the 'big' 75108. With two separate packages I will be able to use smaller cplds.
> Also XOR gates will be quite good at 90' output, but will not be linear > at needle pulse phase outputs, so if you need 360' phase with linearity, > I would suggest look at dual quadrature XOR phase comparisons. > (so one is in mid scale, when the other hits the edges)
Basically that is the reason for dividing by 4 but I did not mention the additional quadrature outputs. The circuit is indeed exactly as you suggest. It has an small microcontroller that looks at the voltages of two quadrature phase comparators with an LTC2402, chooses which is the more appropiate one to use and automatically corrects for the 'jump' in phase when switching between the quadrature outputs. All of this works even better than expected. It is just that the cpld which has not been suspected at all as an possible source of problems now turnes out to be the true beast.
> This stuff is NOT on the chip designer's radar :)
Surely not! Nor has it been on the radar of the designers of the MECL gates that HP used to build their K34-5991A linear phase comparator from! But sometimes using digital stuff for analogue purposes and vice versa can be very funny and shows that the difference is sometimes not that strict.
> Any edge that is very close to another, WILL move the threshold, and > so cause phase non-linearities.
Yes, from some earlier experiments I would have suspected & accepted THIS. But the error function that I tried to describe covers the COMPLETE range of phase-relationships that the two signals can have and that is what makes me wonder. If you supply an address to where I can send something I will be glad to send you an image of it. Best regards Ulrich Bangert "Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag news:46839488$1@clear.net.nz...
> Ulrich Bangert wrote: > > Gents, > > > > please allow me to confront you with some strange timing behaviour which
I
> > have measured with an Xilinx XC95108 cpld. > > > > Consider two well conditioned clock signals of 10 MHz (both having
EXACTLY
> > the same frequency) entering the cpld. Inside the cpld each clock signal
is
> > divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz
signals
> > enter an exclusive-or-gate which delivers an output signal where the > > pulse/pause-relationship directly depends on the phase relationship of
the
> > two input clocks. > > > > If some of you feel reminded to something that you have seen before:
Yes,
> > basically this is the principle of an so called linear phase comparator > > which has been used to compare high stability clocks (for example cesium > > clocks) against each other before high resolution time interval counters > > like the HP5370 or the Stanford Research SR620 were available. > > > > Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is
a
> > bit beyond the discussion HOW this is achieved but you may believe me
that
> > this is possible and that THIS is not part of the discussed problem. Now
the
> > phase relationship of the clocks changes slowly in time as does the > > pulse/pause relationship behind the xor gate. The pulse/pause
relationship
> > of the xor's output can be measured by two completely different methods: > > > > a) by generating an dc voltage which is directly proportional to the > > pulse/pause relationship (again a bit tricky if you want it to be an
really
> > high resolution measurement, but it can be done) > > > > b) by directly measuring the output pulse width with an high resolution
time
> > interval counter like the SR620 having a 25 ps single shot resolution
for
> > time interval measurements. > > > > It is important to note that both methods to measure can be applied at
the
> > same time and that both methods (although based on completely different > > physical laws) deliver results that despite some statistical
fluctuations
> > are basically the same. That is why I am pretty sure that what I measure
is
> > really an property of the signal itself and not one of the measurement > > apparatus. > > > > If I record the pulse width over time using the two methods and display
it
> > graphically it looks like an pretty linear relationship at the first
glance.
> > If however some math is applied to make it evident how good the linear > > relationship really is met then the result is that there are
fluctuations in
> > the pulse width in the order of some +/-450 ps from the expected values. > > > > About these fluctuations the following facts are known: > > > > 1) They are not existent in the inputs clocks > > > > 2) Expressed in time units as well as expressed as an dc voltage the > > fluctuations are orders of magnitude bigger than the resolution and > > precision of the time/dc measurement. > > > > 3) The fluctuations are by no means of stochastical nature. Instead, If
an
> > positive fluctuation is noticed at an certain phase between the clock > > signals, an fluctuation of the same magnitude and sign will be noticed
the
> > next time when the clock signals have the same phase relationship. Or in > > other words: The pulse width is an direct function of the phase
relationship
> > of the clocks + an error function which is an direct function of the
phase
> > relationship between the clocks. > > How often do you see this, 4 or 8 times per 2.5MHz cycle ? > > > > > It seems as if the phase state of one of the signals can have an linear
like
> > modulating effect on the phase state of the second signal (and perhaps
vice
> > versa). Some of you may come to the conclusion that +/-450 ps is not an > > number to cause real world troubles but in my case: The whole
arrangement
> > has the intention to measure phase fluctuations of the input clocks that
ARE
> > REALLY THERE but that are smaller at least one order of magnitude than
the
> > noticed errors. And that is why +/-450 ps is an real annoying number for
me.
> > > > Any hint will be highly appreciated > > TIA, Ulrich Bangert > > I think I have followed this. > If you are trying to 'zoom into' the phase to high precisons, using > analog Phase integration, there are some rules to follow. > > Vcc and Gnd must be VERY clean. > That means no other clocks, and /4 is going to cause more edges and > bounce, plus Vdd impedance noise is usually quite bad on CPLDs. > Any edge that is very close to another, WILL move the threshold, and > so cause phase non-linearities. > Normally, these are so small, well under Tpd, so in the digital domain > they do not matter much. [Some CPLDs will show Tpd delta, vs outputs
loded ]
> > This stuff is NOT on the chip designer's radar :) > > So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, > preferable with Schmitt. eg LVC1G97, with analog Supply decoupling. > > You may even find, you cannot have both non-locked frequencies in the > same package, so may need separate /4 blocks > > Also XOR gates will be quite good at 90' output, but will not be linear > at needle pulse phase outputs, so if you need 360' phase with linearity, > I would suggest look at dual quadrature XOR phase comparisons. > (so one is in mid scale, when the other hits the edges) > ( or even more phases, 4 would be simple from 10MHz, and use 4 ADC > channels - then 3 of the 4 would be low-error ) > > -jg >
Ulrich Bangert wrote:
> Jim, > > thanks for your remarks! Because I did not want to make it too difficult I > simplified my explanation a bit and left out some things that I regarded not > significant for the problem: It is NOT the cpld's xor output directly that I > am trying to integrate, which would be really very difficult with the > intended precision. > > Instead this output merely drives an precision high speed diode based switch > built from some HSMS-2812 which connects an summing rc-element alternating > with two reference voltages that are indeed of highest quality in terms of > precicion, tempco and 'clean-ness' and yes, low impedance. While this > analogue circuitry has been suspected to be the source of problems it has > now (where the direct comparison with the TIC based measurments was > possible) turned out to work like charming. > > >>So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, >>preferable with Schmitt. eg LVC1G97, with analog Supply decoupling. > > > Using an external xor will be the next thing that I am going to try. > However, even this external xor will only drive the switch described above > and therefore its supply will be less critical than you suggest. Because I > am out for speed (10 MHz may not be the highest frequencies to compare) I > ordered some 74AHC1G86 from Farnell. Do you think that the LVC part could be > the better performer due to the Schmitt trigger?
The LVC devices have lower impedances, so would be able to drive Analog-out more easily. (but you can get AHC/HC versions too, so easy to try both ) You may be able to dispense with the down stream analog complexity, by moving the precision ref supplies to the XOR. Try both.
> > >>You may even find, you cannot have both non-locked frequencies in the >>same package, so may need separate /4 blocks > > > This will be the next-next thing to do. Again I simplified a bit: The divide > by 4 flip-flops are the things that provide symmetrical quadrature outputs. > In front of them are programmable predividers that enable the circuit to > compare two signals of not the same frequency. However for the experiment > described these predividers were de-activated. These predividers are the > reason for using the 'big' 75108. With two separate packages I will be able > to use smaller cplds. > > >>Also XOR gates will be quite good at 90' output, but will not be linear >>at needle pulse phase outputs, so if you need 360' phase with linearity, >>I would suggest look at dual quadrature XOR phase comparisons. >>(so one is in mid scale, when the other hits the edges) > > > Basically that is the reason for dividing by 4 but I did not mention the > additional quadrature outputs. The circuit is indeed exactly as you suggest. > It has an small microcontroller that looks at the voltages of two quadrature > phase comparators with an LTC2402, chooses which is the more appropiate one > to use and automatically corrects for the 'jump' in phase when switching > between the quadrature outputs. All of this works even better than expected. > It is just that the cpld which has not been suspected at all as an possible > source of problems now turnes out to be the true beast.
Think of digital sigals as having finite edges, and ALL edges as generating threshold shifts due to the common mode inductances, and you can see the ease with which jitter/crosstalk can get into a system.
> > >>This stuff is NOT on the chip designer's radar :) > > > Surely not! Nor has it been on the radar of the designers of the MECL gates > that HP used to build their K34-5991A linear phase comparator from! But > sometimes using digital stuff for analogue purposes and vice versa can be > very funny and shows that the difference is sometimes not that strict. > > >>Any edge that is very close to another, WILL move the threshold, and >>so cause phase non-linearities. > > > Yes, from some earlier experiments I would have suspected & accepted THIS. > But the error function that I tried to describe covers the COMPLETE range of > phase-relationships that the two signals can have and that is what makes me > wonder. If you supply an address to where I can send something I will be > glad to send you an image of it.
should make interesting viewing : jim dot granville at designtools d o t co d o t nz
> > Best regards > Ulrich Bangert > > "Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag > news:46839488$1@clear.net.nz... > >>Ulrich Bangert wrote: >> >>>Gents, >>> >>>please allow me to confront you with some strange timing behaviour which > > I > >>>have measured with an Xilinx XC95108 cpld. >>> >>>Consider two well conditioned clock signals of 10 MHz (both having > > EXACTLY > >>>the same frequency) entering the cpld. Inside the cpld each clock signal > > is > >>>divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz > > signals > >>>enter an exclusive-or-gate which delivers an output signal where the >>>pulse/pause-relationship directly depends on the phase relationship of > > the > >>>two input clocks. >>> >>>If some of you feel reminded to something that you have seen before: > > Yes, > >>>basically this is the principle of an so called linear phase comparator >>>which has been used to compare high stability clocks (for example cesium >>>clocks) against each other before high resolution time interval counters >>>like the HP5370 or the Stanford Research SR620 were available. >>> >>>Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is > > a > >>>bit beyond the discussion HOW this is achieved but you may believe me > > that > >>>this is possible and that THIS is not part of the discussed problem. Now > > the > >>>phase relationship of the clocks changes slowly in time as does the >>>pulse/pause relationship behind the xor gate. The pulse/pause > > relationship > >>>of the xor's output can be measured by two completely different methods: >>> >>>a) by generating an dc voltage which is directly proportional to the >>>pulse/pause relationship (again a bit tricky if you want it to be an > > really > >>>high resolution measurement, but it can be done) >>> >>>b) by directly measuring the output pulse width with an high resolution > > time > >>>interval counter like the SR620 having a 25 ps single shot resolution > > for > >>>time interval measurements. >>> >>>It is important to note that both methods to measure can be applied at > > the > >>>same time and that both methods (although based on completely different >>>physical laws) deliver results that despite some statistical > > fluctuations > >>>are basically the same. That is why I am pretty sure that what I measure > > is > >>>really an property of the signal itself and not one of the measurement >>>apparatus. >>> >>>If I record the pulse width over time using the two methods and display > > it > >>>graphically it looks like an pretty linear relationship at the first > > glance. > >>>If however some math is applied to make it evident how good the linear >>>relationship really is met then the result is that there are > > fluctuations in > >>>the pulse width in the order of some +/-450 ps from the expected values. >>> >>>About these fluctuations the following facts are known: >>> >>>1) They are not existent in the inputs clocks >>> >>>2) Expressed in time units as well as expressed as an dc voltage the >>>fluctuations are orders of magnitude bigger than the resolution and >>>precision of the time/dc measurement. >>> >>>3) The fluctuations are by no means of stochastical nature. Instead, If > > an > >>>positive fluctuation is noticed at an certain phase between the clock >>>signals, an fluctuation of the same magnitude and sign will be noticed > > the > >>>next time when the clock signals have the same phase relationship. Or in >>>other words: The pulse width is an direct function of the phase > > relationship > >>>of the clocks + an error function which is an direct function of the > > phase > >>>relationship between the clocks. >> >>How often do you see this, 4 or 8 times per 2.5MHz cycle ? >> >> >>>It seems as if the phase state of one of the signals can have an linear > > like > >>>modulating effect on the phase state of the second signal (and perhaps > > vice > >>>versa). Some of you may come to the conclusion that +/-450 ps is not an >>>number to cause real world troubles but in my case: The whole > > arrangement > >>>has the intention to measure phase fluctuations of the input clocks that > > ARE > >>>REALLY THERE but that are smaller at least one order of magnitude than > > the > >>>noticed errors. And that is why +/-450 ps is an real annoying number for > > me. > >>>Any hint will be highly appreciated >>>TIA, Ulrich Bangert >> >>I think I have followed this. >>If you are trying to 'zoom into' the phase to high precisons, using >>analog Phase integration, there are some rules to follow. >> >>Vcc and Gnd must be VERY clean. >>That means no other clocks, and /4 is going to cause more edges and >>bounce, plus Vdd impedance noise is usually quite bad on CPLDs. >>Any edge that is very close to another, WILL move the threshold, and >>so cause phase non-linearities. >>Normally, these are so small, well under Tpd, so in the digital domain >>they do not matter much. [Some CPLDs will show Tpd delta, vs outputs > > loded ] > >>This stuff is NOT on the chip designer's radar :) >> >>So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, >>preferable with Schmitt. eg LVC1G97, with analog Supply decoupling. >> >>You may even find, you cannot have both non-locked frequencies in the >>same package, so may need separate /4 blocks >> >>Also XOR gates will be quite good at 90' output, but will not be linear >>at needle pulse phase outputs, so if you need 360' phase with linearity, >>I would suggest look at dual quadrature XOR phase comparisons. >>(so one is in mid scale, when the other hits the edges) >>( or even more phases, 4 would be simple from 10MHz, and use 4 ADC >>channels - then 3 of the 4 would be low-error ) >> >>-jg >> > > >
On Jun 28, 1:00 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:

> So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, > preferable with Schmitt. eg LVC1G97, with analog Supply decoupling.
Actually, this might not be sufficient. The clock-to-out delay of the flip-flops in the CPLD and of the output drivers of the CPLD depend on the supply voltage. The supply voltage inside the chip depends on the switching history of all nearby signals in the chip. (E.G. the carry chain delay of a Spartan-2 doubles during an interval of a few hundred picoseconds after the flip-flops connected to it were switching.) Similar is true for the input thresholds of the flip flop clock inputs. At the precisions you are talking about you will see a lot of crosstalk from different sources. It surely will help to use discrete fast flip-flops instead of a CPLD (We use PECL devices from OnSemi). At least you don't see package ground bounce across packages. Another option is to measure the positions of the edges individually and compute the phase difference from that. Many Time To Digital Converters have two or more channels. See our website www.cronologic.de for an example. Kolja Sulimma
Kolja,

I needed only a vague look to your website to see that you surely know what
you are talking about. Yes, clearly an TDC can be used for that purpose. My
efforts to do it the linear way have the background to make an very cheap
technology available that would enable say radio amateurs to characterize
precise oscillators. In terms of price the modern cplds come very handy.
I will think about your suggestions.

Best regards
Ulrich Bangert

Best regards
Ulrich Bangert
"comp.arch.fpga" <ksulimma@googlemail.com> schrieb im Newsbeitrag
news:1183106805.864519.234350@q75g2000hsh.googlegroups.com...
> On Jun 28, 1:00 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > > So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, > > preferable with Schmitt. eg LVC1G97, with analog Supply decoupling. > > Actually, this might not be sufficient. The clock-to-out delay of the > flip-flops in the CPLD and > of the output drivers of the CPLD depend on the supply voltage. The > supply voltage inside > the chip depends on the switching history of all nearby signals in the > chip. > (E.G. the carry chain delay of a Spartan-2 doubles during an interval > of a few hundred picoseconds > after the flip-flops connected to it were switching.) > > Similar is true for the input thresholds of the flip flop clock > inputs. At the precisions you are talking about > you will see a lot of crosstalk from different sources. > > It surely will help to use discrete fast flip-flops instead of a CPLD > (We use PECL devices from OnSemi). > At least you don't see package ground bounce across packages. > > Another option is to measure the positions of the edges individually > and compute the phase difference from that. Many Time To Digital > Converters have two or more channels. See our website www.cronologic.de > for an example. > > Kolja Sulimma > >
On Thu, 28 Jun 2007 11:02:38 +0200, "Ulrich Bangert"
<df6jb@ulrich-bangert.de> wrote:

>Gents, > >please allow me to confront you with some strange timing behaviour which I >have measured with an Xilinx XC95108 cpld. > >Consider two well conditioned clock signals of 10 MHz (both having EXACTLY >the same frequency) entering the cpld. Inside the cpld each clock signal is >divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz signals >enter an exclusive-or-gate which delivers an output signal where the >pulse/pause-relationship directly depends on the phase relationship of the >two input clocks. > >If some of you feel reminded to something that you have seen before: Yes, >basically this is the principle of an so called linear phase comparator >which has been used to compare high stability clocks (for example cesium >clocks) against each other before high resolution time interval counters >like the HP5370 or the Stanford Research SR620 were available. > >Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is a >bit beyond the discussion HOW this is achieved but you may believe me that >this is possible and that THIS is not part of the discussed problem. Now the >phase relationship of the clocks changes slowly in time as does the >pulse/pause relationship behind the xor gate. The pulse/pause relationship >of the xor's output can be measured by two completely different methods: > >a) by generating an dc voltage which is directly proportional to the >pulse/pause relationship (again a bit tricky if you want it to be an really >high resolution measurement, but it can be done) > >b) by directly measuring the output pulse width with an high resolution time >interval counter like the SR620 having a 25 ps single shot resolution for >time interval measurements. > >It is important to note that both methods to measure can be applied at the >same time and that both methods (although based on completely different >physical laws) deliver results that despite some statistical fluctuations >are basically the same. That is why I am pretty sure that what I measure is >really an property of the signal itself and not one of the measurement >apparatus. > >If I record the pulse width over time using the two methods and display it >graphically it looks like an pretty linear relationship at the first glance. >If however some math is applied to make it evident how good the linear >relationship really is met then the result is that there are fluctuations in >the pulse width in the order of some +/-450 ps from the expected values. > >About these fluctuations the following facts are known: > >1) They are not existent in the inputs clocks > >2) Expressed in time units as well as expressed as an dc voltage the >fluctuations are orders of magnitude bigger than the resolution and >precision of the time/dc measurement. > >3) The fluctuations are by no means of stochastical nature. Instead, If an >positive fluctuation is noticed at an certain phase between the clock >signals, an fluctuation of the same magnitude and sign will be noticed the >next time when the clock signals have the same phase relationship. Or in >other words: The pulse width is an direct function of the phase relationship >of the clocks + an error function which is an direct function of the phase >relationship between the clocks. > >It seems as if the phase state of one of the signals can have an linear like >modulating effect on the phase state of the second signal (and perhaps vice >versa). Some of you may come to the conclusion that +/-450 ps is not an >number to cause real world troubles but in my case: The whole arrangement >has the intention to measure phase fluctuations of the input clocks that ARE >REALLY THERE but that are smaller at least one order of magnitude than the >noticed errors. And that is why +/-450 ps is an real annoying number for me. > >Any hint will be highly appreciated >TIA, Ulrich Bangert > > >
Sounds like crosstalk internal to the cpld, and likely the fact that the xor gate behaves differently in the case where one edge changes, as opposed to when both edges change simultaneously. I'd suggest using discrete logic, ECL or Eclips for serious performance. A d-type flipflop makes a good phase detector, too. John
Note, that as long as there is no other logic inside the CPLD, the
result for an individual chip should be very predictable. You can
measure and correct the nonlinearity. If there is a big difference
from chip to chip you need to calibrate the correction for each chip.
There might be a significant dependance on tempereture. In that case
you would have to ovenize the thing which is probably more expensive
than the discrete solution. I am sure that extremly fast ECL logic
works well, but I am not sure how important that is. Maybe CMOS single
gate logic with a very clean power supply is good enough. In that case
the logic would be very small and even less expensive than the CPLD.

Kolja Sulimma

On Jun 29, 1:44 pm, "Ulrich Bangert" <d...@ulrich-bangert.de> wrote:
> Kolja, > > I needed only a vague look to your website to see that you surely know what > you are talking about. Yes, clearly an TDC can be used for that purpose. My > efforts to do it the linear way have the background to make an very cheap > technology available that would enable say radio amateurs to characterize > precise oscillators. In terms of price the modern cplds come very handy. > I will think about your suggestions. > > Best regards > Ulrich Bangert > > Best regards > Ulrich Bangert > "comp.arch.fpga" <ksuli...@googlemail.com> schrieb im Newsbeitragnews:1183106805.864519.234350@q75g2000hsh.googlegroups.com... > > > On Jun 28, 1:00 pm, Jim Granville <no.s...@designtools.maps.co.nz> > > wrote: > > > > So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, > > > preferable with Schmitt. eg LVC1G97, with analog Supply decoupling. > > > Actually, this might not be sufficient. The clock-to-out delay of the > > flip-flops in the CPLD and > > of the output drivers of the CPLD depend on the supply voltage. The > > supply voltage inside > > the chip depends on the switching history of all nearby signals in the > > chip. > > (E.G. the carry chain delay of a Spartan-2 doubles during an interval > > of a few hundred picoseconds > > after the flip-flops connected to it were switching.) > > > Similar is true for the input thresholds of the flip flop clock > > inputs. At the precisions you are talking about > > you will see a lot of crosstalk from different sources. > > > It surely will help to use discrete fast flip-flops instead of a CPLD > > (We use PECL devices from OnSemi). > > At least you don't see package ground bounce across packages. > > > Another option is to measure the positions of the edges individually > > and compute the phase difference from that. Many Time To Digital > > Converters have two or more channels. See our websitewww.cronologic.de > > for an example. > > > Kolja Sulimma
Gents,

this is to let you know that departing the two clock signals into two
separate cplds and xoring them with external single-gate-logic has improved
the situation a lot.

Thank you for your suggestions.
Ulrich Bangert

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im
Newsbeitrag news:lbkb83pbag42itmtl43up1h11gt2566124@4ax.com...
> On Thu, 28 Jun 2007 11:02:38 +0200, "Ulrich Bangert" > <df6jb@ulrich-bangert.de> wrote: > > >Gents, > > > >please allow me to confront you with some strange timing behaviour which
I
> >have measured with an Xilinx XC95108 cpld. > > > >Consider two well conditioned clock signals of 10 MHz (both having
EXACTLY
> >the same frequency) entering the cpld. Inside the cpld each clock signal
is
> >divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz
signals
> >enter an exclusive-or-gate which delivers an output signal where the > >pulse/pause-relationship directly depends on the phase relationship of
the
> >two input clocks. > > > >If some of you feel reminded to something that you have seen before: Yes, > >basically this is the principle of an so called linear phase comparator > >which has been used to compare high stability clocks (for example cesium > >clocks) against each other before high resolution time interval counters > >like the HP5370 or the Stanford Research SR620 were available. > > > >Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is
a
> >bit beyond the discussion HOW this is achieved but you may believe me
that
> >this is possible and that THIS is not part of the discussed problem. Now
the
> >phase relationship of the clocks changes slowly in time as does the > >pulse/pause relationship behind the xor gate. The pulse/pause
relationship
> >of the xor's output can be measured by two completely different methods: > > > >a) by generating an dc voltage which is directly proportional to the > >pulse/pause relationship (again a bit tricky if you want it to be an
really
> >high resolution measurement, but it can be done) > > > >b) by directly measuring the output pulse width with an high resolution
time
> >interval counter like the SR620 having a 25 ps single shot resolution for > >time interval measurements. > > > >It is important to note that both methods to measure can be applied at
the
> >same time and that both methods (although based on completely different > >physical laws) deliver results that despite some statistical fluctuations > >are basically the same. That is why I am pretty sure that what I measure
is
> >really an property of the signal itself and not one of the measurement > >apparatus. > > > >If I record the pulse width over time using the two methods and display
it
> >graphically it looks like an pretty linear relationship at the first
glance.
> >If however some math is applied to make it evident how good the linear > >relationship really is met then the result is that there are fluctuations
in
> >the pulse width in the order of some +/-450 ps from the expected values. > > > >About these fluctuations the following facts are known: > > > >1) They are not existent in the inputs clocks > > > >2) Expressed in time units as well as expressed as an dc voltage the > >fluctuations are orders of magnitude bigger than the resolution and > >precision of the time/dc measurement. > > > >3) The fluctuations are by no means of stochastical nature. Instead, If
an
> >positive fluctuation is noticed at an certain phase between the clock > >signals, an fluctuation of the same magnitude and sign will be noticed
the
> >next time when the clock signals have the same phase relationship. Or in > >other words: The pulse width is an direct function of the phase
relationship
> >of the clocks + an error function which is an direct function of the
phase
> >relationship between the clocks. > > > >It seems as if the phase state of one of the signals can have an linear
like
> >modulating effect on the phase state of the second signal (and perhaps
vice
> >versa). Some of you may come to the conclusion that +/-450 ps is not an > >number to cause real world troubles but in my case: The whole arrangement > >has the intention to measure phase fluctuations of the input clocks that
ARE
> >REALLY THERE but that are smaller at least one order of magnitude than
the
> >noticed errors. And that is why +/-450 ps is an real annoying number for
me.
> > > >Any hint will be highly appreciated > >TIA, Ulrich Bangert > > > > > > > > Sounds like crosstalk internal to the cpld, and likely the fact that > the xor gate behaves differently in the case where one edge changes, > as opposed to when both edges change simultaneously. > > I'd suggest using discrete logic, ECL or Eclips for serious > performance. > > A d-type flipflop makes a good phase detector, too. > > John >
Ulrich Bangert wrote:

> Gents, > > this is to let you know that departing the two clock signals into two > separate cplds and xoring them with external single-gate-logic has improved > the situation a lot.
Good to hear that :) Can you quantify "improved the situation a lot", so readers can know what the relative jitter levels are ? Which/how many single gate devices did you use ? & which CPLDs ? -jg