Multiplier in Xilinx

I have a problem about the data width of the output of multiplier.
I am using the coregen Multiplier in Xilinx.
a : std_logic_vector(3 downto 0);
b : std_logic_vector(15 downto 0);
q:  std_logic_vector(15 downto 0);

I simulated the result by using Modelsim. I found 'q' cannot get
correct result unless I change the width of 'q' to 19.

I want to know if it is possible to get 16 bit accurate result.
Because i need 'q' to connect to another input port with 16 bits
width.

One more thing, Is the modelsim can simulate the delay time for the
Coregen Multiplier. I have pre-define the parameters of the Multiplier
to make the latency is zero. Why I see the result of 'q' is shown with
a long delay  after the input 'a' 'b' are written into the port.

Any comment about the multiplier is appreciated. Thank you.

ZHI wrote:
> I have a problem about the data width of the output of multiplier.
> I am using the coregen Multiplier in Xilinx.
> a : std_logic_vector(3 downto 0);
> b : std_logic_vector(15 downto 0);
> q:  std_logic_vector(15 downto 0);
> 
> I simulated the result by using Modelsim. I found 'q' cannot get
> correct result unless I change the width of 'q' to 19.
> 
> I want to know if it is possible to get 16 bit accurate result.
> Because i need 'q' to connect to another input port with 16 bits
> width.
> 
> One more thing, Is the modelsim can simulate the delay time for the
> Coregen Multiplier. I have pre-define the parameters of the Multiplier
> to make the latency is zero. Why I see the result of 'q' is shown with
> a long delay  after the input 'a' 'b' are written into the port.
> 
> Any comment about the multiplier is appreciated. Thank you.


What's 65535 * 15 ?

It is for my parameter update. A=N*Lamda, N is iternation number from
1 to 5, and the Lamda is a number in 'std_logic_vector(15 downto 0)'.
A1=1*lamda,A2=2*lamda,A3=3*Lamda,....The multiplier deals with the
number with the type 'signed'/'unsigned'. So i change the 2 parameter
to the std_logic_vector.
That is why i use 65535 * 15.
I want to know if i only need 16bits for the output, how to do it.
thanks.
John_H wrote:
> ZHI wrote:
> > I have a problem about the data width of the output of multiplier.
> > I am using the coregen Multiplier in Xilinx.
> > a : std_logic_vector(3 downto 0);
> > b : std_logic_vector(15 downto 0);
> > q:  std_logic_vector(15 downto 0);
> >
> > I simulated the result by using Modelsim. I found 'q' cannot get
> > correct result unless I change the width of 'q' to 19.
> >
> > I want to know if it is possible to get 16 bit accurate result.
> > Because i need 'q' to connect to another input port with 16 bits
> > width.
> >
> > One more thing, Is the modelsim can simulate the delay time for the
> > Coregen Multiplier. I have pre-define the parameters of the Multiplier
> > to make the latency is zero. Why I see the result of 'q' is shown with
> > a long delay  after the input 'a' 'b' are written into the port.
> >
> > Any comment about the multiplier is appreciated. Thank you.
>
>
> What's 65535 * 15 ?

"ZHI" <threeinchnail@gmail.com> wrote in message 
news:1183386642.801925.162180@q69g2000hsb.googlegroups.com...
> It is for my parameter update. A=N*Lamda, N is iternation number from
> 1 to 5, and the Lamda is a number in 'std_logic_vector(15 downto 0)'.
> A1=1*lamda,A2=2*lamda,A3=3*Lamda,....The multiplier deals with the
> number with the type 'signed'/'unsigned'. So i change the 2 parameter
> to the std_logic_vector.
> That is why i use 65535 * 15.
> I want to know if i only need 16bits for the output, how to do it.
> thanks.


I asked you the leading question and you gave me background, not an answer.

16'hffff * 4'hf = 20'hefff1
(16'd65535 * 4'd15 = 20'd983025)

The 20-bit value efff1 cannot be represented in 16 bits.

The question you need to ask yourself is what accuracy you need in your 
parameter value that you're trying to restrict to 16 bits.  Perhaps you can 
get by with 9 bits.  It's ENTIRELY dependent on your needs and NOT something 
we can give you advice on without knowing the details of your needs.  The 
details you gave only give a glimpse at issues that are probably too 
detailed to communicate effectively online.

Are you familiar with the concepts of Error Analysis and Quantization Error?

- John_H

ZHI wrote:
> I want to know if i only need 16bits for the output, how to do it.
> thanks.

You are dealing with binary fractions, not integers, right? That is, 
numbers between 0 and 1 (or -1 to 1)? In your case, just take the 
leftmost 16 bits of the 20 bit result.

-Jeff

On 2 Jul, 17:39, Jeff Cunningham <j...@sover.net> wrote:
> ZHI wrote:
> > I want to know if i only need 16bits for the output, how to do it.
> > thanks.
>
> You are dealing with binary fractions, not integers, right? That is,
> numbers between 0 and 1 (or -1 to 1)? In your case, just take the
> leftmost 16 bits of the 20 bit result.
>
> -Jeff

No, i am dealing with integers and binary fractions. I cannot only
take the leftmost 16bits. It will result in the wrong.

ZHI wrote:
> On 2 Jul, 17:39, Jeff Cunningham <j...@sover.net> wrote:
>> ZHI wrote:
>>> I want to know if i only need 16bits for the output, how to do it.
>>> thanks.
>> You are dealing with binary fractions, not integers, right? That is,
>> numbers between 0 and 1 (or -1 to 1)? In your case, just take the
>> leftmost 16 bits of the 20 bit result.
>>
>> -Jeff
> 
> No, i am dealing with integers and binary fractions. I cannot only
> take the leftmost 16bits. It will result in the wrong.
> 

Then either :
 - Your application ensure by design that the result is always
   smaller than 65535 and you can just take the rightmost 16 bits.
 - You must have a result on 20 bits (deal with it !)
 - You're screwed


	Sylvain

> > You are dealing with binary fractions, not integers, right? That is,
> > numbers between 0 and 1 (or -1 to 1)? In your case, just take the
> > leftmost 16 bits of the 20 bit result.
>

I am coming into this discussion late, but if you ha 20 bit result
(prod[19:0]) from a 4 and 16 bit signed fractional mult, you would
want to keep prod[18:3] to keep it in the range of -1 to 1. You end up
with two sign bits when you multiply two signed fractions together so
you can throw one of them away.

Note, you should also have a rounding scheme for prod[2:0] to keep it
as accurate as possible.

Tom

The multipliers in Altera Stratix FPGAs can be operated in a Q1.15
fractional binary mode that I have found to be useful in a previous
project.

If the Xilinx multipliers can be operated in a similar mode it might be
a/the answer to your problem.

RCIngham wrote:
> The multipliers in Altera Stratix FPGAs can be operated in a Q1.15
> fractional binary mode that I have found to be useful in a previous
> project.
>
> If the Xilinx multipliers can be operated in a similar mode it might be
> a/the answer to your problem.


Thanks for all your answers. 'lamda' is within (-1,1) and  transmitted
into fpga board from matalab. Before it transmitted to uart, lamda has
been changed to Q15 format. I need 'lamda' update correspording to the
interative times from 1 to 5. I guess I am wrong here. I cannot direct
use the integer * Q15 binary. Coz the 'lamda' is binary and has been
enlarged 2*16 whereas interative number is not.

I did not  know  how to figure it out so far. So can I just generate
the 5 interative numbers and multiply from matlab and transformed to
Q15 format, then transmit to the fpga. (It looks so silly)

Also the Q15 updated lamda will mulitply another Q15 parameter.  2
signed prod[15 0] multiply. If I want to keep 32 bits. Is it correct
that I just keep prod[30 0] & '0' as my result. I removed the first
sign.

One more thing, the type in the multiplier is 'signed', why i still
can use 'std_logic_vector'. Is it same?  And I don't need to convert
'std_logic_vector' to 'signed'.