Spartan-3e JTAG no device id

Alan,

No, this is not an issue of the ramp of any supplies....

I would look for something very simple, and basic, like an open, or a short.

Austin

Alan,

Mode pins have no effect on JTAG.

Austin

Alan,

http://direct.xilinx.com/bvdocs/userguides/ug332.pdf

On page 184, it details the settings for Vccaux 2.5 volt powering of the 
JTAG.  Perhaps, this being the only difference with V2 Pro, this may 
need to be looked into?

Also, the INIT should go low, and then once the device has cleaned out, 
and is ready to be configured, INIT will return high (requires a pull-up 
resistor).

Holding INIT low, continues the cleanout, and prevents any further 
operation (until it is released).

I am not sure, but it may be that as long as INIT is low, the JTAG state 
machine may not be operating (..?..).

Austin

Alan Nishioka wrote:
> I have tried changing the mode pins (difficult because they are
> connected directly to V33 and gnd) to no effect.  But JTAG should work
> regardless of the mode pin settings, right?

Yes, JTAG works in all modes. And maybe you have the mode pins set to 
salve serial. Or even floating, which means that the default pullups 
pull them to slave serial, depending on the HSWAP pin.

What I was suggesting is that you try programming the part in slave 
serial mode. That could show up any one of a host of problems. If slave 
serial works and JTAG doesn't...

Good luck.

Alan,

INIT is not the signal that holds the JTAG block in reset, it is the 
PROG signal, or the power ON reset.

So, if the core voltage AND the Vccaux AND the IO bank which has the 
config pins on it are all powered ON, AND if the PROG_b is not being 
intentionally held low, THEN the JTAG state machine should be released, 
and should operate.  Basically, when INIT goes high, the mode pins are 
sampled, and then based on the mode pins, the configuration state 
machine goes to whatever mode is specified, and proceeds with configuration.

If JTAG is specified by the mode pins, then the part waits to be 
configured through the JTAG port.

JTAG device ID can be read out prior to configuring (by any mode).

Amazing what digging through the schematics reveals.

Austin

On Jul 3, 1:54 pm, "Tim (one of many)"
<t...@nooospam.roockyloogic.com> wrote:
> Alan Nishioka wrote:
> > I have tried changing the mode pins (difficult because they are
> > connected directly to V33 and gnd) to no effect.  But JTAG should work
> > regardless of the mode pin settings, right?
>
> Yes, JTAG works in all modes. And maybe you have the mode pins set to
> salve serial. Or even floating, which means that the default pullups
> pull them to slave serial, depending on the HSWAP pin.
>
> What I was suggesting is that you try programming the part in slave
> serial mode. That could show up any one of a host of problems. If slave
> serial works and JTAG doesn't...
>
> Good luck.


Thank you all for your ideas.  I now have a few more things to try.

Alan Nishioka

On Jul 3, 2:03 pm, austin <aus...@xilinx.com> wrote:
> INIT is not the signal that holds the JTAG block in reset, it is the
> PROG signal, or the power ON reset.
>
> So, if the core voltage AND the Vccaux AND the IO bank which has the
> config pins on it are all powered ON, AND if the PROG_b is not being
> intentionally held low, THEN the JTAG state machine should be released,
> and should operate.  Basically, when INIT goes high, the mode pins are
> sampled, and then based on the mode pins, the configuration state
> machine goes to whatever mode is specified, and proceeds with configuration.
>
> If JTAG is specified by the mode pins, then the part waits to be
> configured through the JTAG port.
>
> JTAG device ID can be read out prior to configuring (by any mode).
>
> Amazing what digging through the schematics reveals.
>
> Austin

I tried tying PROG_B to gnd on my working virtex-2p board, and
identify works fine (JTAG reads device id okay).

Is there any reason to expect spartan-3e to behave differently from
virtex-2p in this respect?

I also tried using a bench power supply for vint (in case my on board
supply was bad), but this made no difference.

My next thought is I fried the chip in some weird way and I will try
replacing it.

Alan Nishioka

Alan,

Holding PROG_b low should hold the JTAG state machine in reset.

I did not check the V2P schematics, so maybe they did something different.

Austin

On Jul 5, 12:26 am, Alan Nishioka <a...@nishioka.com> wrote:
> On Jul 3, 2:03 pm, austin <aus...@xilinx.com> wrote:
>
> My next thought is I fried the chip in some weird way and I will try
> replacing it.
>
> Alan Nishioka- Hide quoted text -
>
> - Show quoted text -

its another try, sure.
I happen to own 3 dead FPGA boards with XC3S100E-TQ144 on them..
they are those "sample pack boards", think there is something badly
wrong with power supply on that board
so I managed to get all 3 boards to fry..

at least one of them was damaged in a way that FPGA was half dead, eg
can configure ok, but not all LUTS work

Antti

I have figured it out.  (well part of it)
I finally tried it with a Platform USB cable belonging to my Avnet
FAE, and it WORKED!

I had been using a Parallel Cable III (I guess I left that out).  I
was certain that this would have no effect.

I still can't explain why JTAG partially works, but won't read device
id.
I would love for someone to confirm this or explain it.

My guess would be some sort of voltage incompatibility (But I was
*sure* changing the cable would have no effect, so how good are my
guesses?)

Thank you to everyone for your suggestions.
Alan Nishioka


On Jul 3, 11:06 am, Alan Nishioka <a...@nishioka.com> wrote:
> I am trying to get an xc3s250e-4tq144c to configure using JTAG.
>
> 1. impact reads 0x00000000 as idcode
>     This causes impact to error out during identify with a strange
> error about missing bsdl's
> 2. JTAG works using impact debug mode.  I can put it in bypass and
> also see the length of the instruction register.  I can see data
> shifting in and out so I know JTAG works.
> 3. Part markings are:
> XC3250E
> TQ144AGQ0601
> D1392255A0
> 4C
> so it is a step 0 part.
> 4.  I have tried impact 8.1.3 and 9.1
> 5.  I get identical results with two pc boards.
> 6.  Same software / computer / cable setup works fine with a virtex2p
> design.
> 7.  All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio)
> 8.  spartan-3e is the only part in the JTAG chain.
>
> I have tried removing all the parts except the spartan and power to
> make sure nothing else was interfering with it.
>
> I have not made any progress with my Avnet FAE and Xilinx webcase so I
> thought to try here.
>
> I have run out of things to try.  Does this look familiar to anyone?
> Any ideas to try?
>
> Alan Nishioka
> a...@nishioka.com