Revisit: Altera vs Xilinx (NIOS II vs Microblaze)

Hi everyone,

No doubt this subject has been discussed on numerous occasions:

http://www.embeddedrelated.com/groups/fpga-cpu/show/2182.php
http://www.edaboard.com/ftopic74807.html
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/d5df4786b2340f21/4502e4fb620f5157?lnk=st&q=microblaze+vs+nios&rnum=2#4502e4fb620f5157
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/e629302f416e08cd/6916d47ebb3868b1?lnk=st&q=microblaze+vs+nios&rnum=3#6916d47ebb3868b1

However it seems that it has been a while since the subject has been 
visited, and since it has been a while, I'm wondering if opinions have 
changed.

I went to a Xilinx sponsored seminar and was impressed by the 
capabilities of the tools, product and the knowledge of the local FAE's. 
  I've since purchased a Spartan 3E Starter Kit to investigate the 
feasibility of using Soft processors to consolidate 4 or so processor 
boards in one of our products.  (couldn't find an Altera Dev kit - not 
saying that one doesn't exist, just could find one - with similar 
features [Ethernet/RS232] in the same price range)

However, I would also like to not exclude Altera/NIOS II from 
consideration based on the fact that I went to a Xilinx seminar and 
found a cheap & cool Development kit!

My main concern isn't the architecture of either core.  More important 
to me are the following factors:

1) Good integration of soft processor with IDE/Tools - intuitive tools
2) Ability to guarantee supply of pin/function compatible parts for long 
term.
3) Abundance of IP bundled with tools (or open source) [eg. I2C, SPI, 
UART, Eth MACS, USB MACS, etc]
4) Cheaper IDE/Tools (I understand Quartus & ISE webpacks are free, but 
neither EDK or Nios II Embedded Design Suite are)
5) Ability to upgrade (Pin/Function compatible) parts with higher/lower 
density parts. (I know for example Spartan 3's are interchangeable 
within each family; Could someone please confirm if Altera's FPGAs have 
this ability)
6) Availability of RTOS/eOS ports to soft processor
7) Abundance of tutorials/how-to's/examples
8) Good community support

My take from what I've read so far is that both Xilinx and Altera are 
good.  Some have said that Quartus is a a little slicker and easier to 
use than ISE - if you've had the opportunity to play with both recently, 
do you still think that is true?

Any insight into the Altera(Nios) vs Xilinx(Microblaze) comparison would 
be greatly appreciated.

Thanks very much for your opinions and insight.
PretzelX.

> 1) Good integration of soft processor with IDE/Tools - intuitive tools

They're both effectively the the same.

> 4) Cheaper IDE/Tools (I understand Quartus & ISE webpacks are free, but
> neither EDK or Nios II Embedded Design Suite are)

If you want a free CPU and cross Vendor compatibility, try the
LatticeMico32.

http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm

> My take from what I've read so far is that both Xilinx and Altera are
> good.  Some have said that Quartus is a a little slicker and easier to
> use than ISE - if you've had the opportunity to play with both recently,
> do you still think that is true?

There's not much in it. All the vendors tools can do the job (most of
the time ;) ).

Cheers,
Jon

PretzelX,

Xilinx recognizes the investment made when choosing a 
processor/architecture/language; and has made every effort to follow the 
"golden rule": Never obsolete your processor.

And, so far, we have never given any customer cause to worry.

There are no plans to (ever) change this policy.

Our track record also speaks to keeping this commitment.

The same can not be said for our competitors.

Austin

austin wrote:
> PretzelX,
> 
> Xilinx recognizes the investment made when choosing a 
> processor/architecture/language; and has made every effort to follow the 
> "golden rule": Never obsolete your processor.

How is it possible to obsolete a soft core?

  -- Mike Treseler

On Jul 5, 1:19 pm, Mike Treseler <mike_trese...@comcast.net> wrote:

> How is it possible to obsolete a soft core?

By offering it in the form of device-specific macros or semi-compiled
descriptions.

Only if the processor core is true "source code" written in terms of
generic or practically duplicatable library objects do you have
immunity from obsolecence.  Otherwise, you are dependent on the
targeted devices continuing to be available, or whoever has the true
source code offering you new versions that work on newer devices, or
some third partner creating a workalike.

Mike,

Easy.  Just introduce a "new and improved" incompatible version, and 
remove support for the old one.

Another way of saying "the original soft processor was so bad, that we 
redesigned it..."

Thankfully, MicroBlaze(tm) soft processors followed the Harvard RISC 
architecture, and we got it right the first time.

But, enough of this venture into the dark and murky realm of choice of 
microprocessor architectures and language.

The biggest, and most important reason to choose a processor is what you 
already have written:  can it be targeted at your choices?

Austin

cs_posting@hotmail.com wrote:

> Only if the processor core is true "source code" written in terms of
> generic or practically duplicatable library objects do you have
> immunity from obsolecence.  Otherwise, you are dependent on the
> targeted devices continuing to be available,

Yes. The device can become obsolete,
but if I have the netlist and the device,
the "processor" usage of the device cannot
be obsoleted.

  -- Mike Treseler

On Jul 5, 4:44 pm, Mike Treseler <mike_trese...@comcast.net> wrote:

> Yes. The device can become obsolete,
> but if I have the netlist and the device,
> the "processor" usage of the device cannot
> be obsoleted.

Only so long as you can buy the devices.  Obsolecence doesn't usually
imply that the devices in your company stock room / desk drawer stop
working, it implies that there aren't and aren't going to be any more
in your distributor's stock room for you to buy.  Or it may imply that
you are locked into using old technology devices and unable to take
advantage of newer ones which may badly needed advantages / ability to
keep up with your market.

At that point, the netlist is only going to help you if you have
alternate-device versions of all of the components that it
instantiates.

austin <austin@xilinx.com> wrote:

>Mike,
>
>Easy.  Just introduce a "new and improved" incompatible version, and 
>remove support for the old one.
>
>Another way of saying "the original soft processor was so bad, that we 
>redesigned it..."
>
>Thankfully, MicroBlaze(tm) soft processors followed the Harvard RISC 
>architecture, and we got it right the first time.

Where I live harvard architecture means exit... Having a seperated
code and data area causes a lot of overhead in software because each
pointer needs to be extended with the memory type it is pointing to.

It also makes the CPU more complicated because you need twice the
amount of memory move instructions which wastes opcode combinations
which could have been used for other usefull instructions for
functions that usually take several instructions (like bit set, clear,
and, or, xor).

And why not use an ARM core? That would have made a lot more sense
than creating something completely new.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Hi,

I think it would be hard to find an ARM core that isn't harvard 
architecture.

Harvard architecture means that the pathways from the CPU are seperate for 
instruction and data.
It doesn't mean that the actual memory needs to be two seperate memories.
In fact the common usage is that the memory is the same.

What Austin was referring to was that Altera went from a different 
architecture/ISA when they moved from NIOS-I to NIOS-II.
All programs needed to be recompiled for NIOS-II and assembler code had to 
manually be translated to NIOS-II assembler instructions.
MicroBlaze has stayed with the same ISA and all new features are optional.
You can take object-code from the first version of MicroBlaze and run it the 
latest version (and in the future versions).

G�ran Bilski

"Nico Coesel" <nico@puntnl.niks> wrote in message 
news:468e6c92.72808603@news.planet.nl...
> austin <austin@xilinx.com> wrote:
>
>>Mike,
>>
>>Easy.  Just introduce a "new and improved" incompatible version, and
>>remove support for the old one.
>>
>>Another way of saying "the original soft processor was so bad, that we
>>redesigned it..."
>>
>>Thankfully, MicroBlaze(tm) soft processors followed the Harvard RISC
>>architecture, and we got it right the first time.
>
> Where I live harvard architecture means exit... Having a seperated
> code and data area causes a lot of overhead in software because each
> pointer needs to be extended with the memory type it is pointing to.
>
> It also makes the CPU more complicated because you need twice the
> amount of memory move instructions which wastes opcode combinations
> which could have been used for other usefull instructions for
> functions that usually take several instructions (like bit set, clear,
> and, or, xor).
>
> And why not use an ARM core? That would have made a lot more sense
> than creating something completely new.
>
> -- 
> Reply to nico@nctdevpuntnl (punt=.)
> Bedrijven en winkels vindt U op www.adresboekje.nl