A Way for a DSP to tell an FPGA to load itself from Flash

Hi,
 my setup is as follows:
1) DSP ADSP-21065L
2) Xilinx xc3s250
3) Intel JS2BF320J3D Flash

I am able to have the DSP load itself from flash but after it's done
loading, I would like the DSP to tell the FPGA to load itself from the
same flash. They will be sharing address and data lines and cannot
operate at the same time.

I am wondering if there is a way for the DSP to tell the FPGA to load
itself from Flash. Is there a special pin on the FPGA for that.
Thanks.
Amish

Amish,

Hold PROG_b low until it is time to configure?  That holds off
configuration until PROG_b is released.

Austin

On Jul 9, 1:39 pm, austin <aus...@xilinx.com> wrote:
> Amish,
>
> Hold PROG_b low until it is time to configure?  That holds off
> configuration until PROG_b is released.
>
> Austin

My concern would be what do the DSP and FPGA pins output when they are
in reset mode or while programing. It would be an issue if both are
driving the address line of the FLASH while one is trying to program
itself.
Amish

Amish,

While PROG_b is held low, all IO is tristate on the FPGA.

Austin

axr0284 wrote:
> On Jul 9, 1:39 pm, austin <aus...@xilinx.com> wrote:
>> Amish,
>>
>> Hold PROG_b low until it is time to configure?  That holds off
>> configuration until PROG_b is released.
>>
>> Austin
> 
> My concern would be what do the DSP and FPGA pins output when they are
> in reset mode or while programing. It would be an issue if both are
> driving the address line of the FLASH while one is trying to program
> itself.
> Amish
> 

> My concern would be what do the DSP and FPGA pins output when they are
> in reset mode or while programing. It would be an issue if both are
> driving the address line of the FLASH while one is trying to program
> itself.
> Amish

	Actually, you're concerned about preventing the FPGA from configuring  
itself and becoming active too early...

	Maybe you can have the DSP configure the FPGA : once it has loaded its  
program from the flash, the DSP can read (at a specific flash address) the  
FPGA bitstream and send it to the FPGA (via SPI, parallel, whatever). This  
way you specify where your bitstream is stored in the flash...

On Jul 9, 6:11 pm, PFC <l...@peufeu.com> wrote:
> > My concern would be what do the DSP and FPGA pins output when they are
> > in reset mode or while programing. It would be an issue if both are
> > driving the address line of the FLASH while one is trying to program
> > itself.
> > Amish
>
>         Actually, you're concerned about preventing the FPGA from configuring  
> itself and becoming active too early...
>
>         Maybe you can have the DSP configure the FPGA : once it has loaded its  
> program from the flash, the DSP can read (at a specific flash address) the  
> FPGA bitstream and send it to the FPGA (via SPI, parallel, whatever). This  
> way you specify where your bitstream is stored in the flash...

This is how it is currently done but then we become dependent on the
DSP to load the code introducing a single point of failure. I would
like to be able to load the code from Flash independently of the DSP
if the DSP stops working.
Amish