Hi Xilinx Killers, It is really annoying to rename and group all the signals everytime when design is modified and new bit file is used to configure the fpga. Anybody knows how to avoid renaming and regrouping signals in the analyzer when new bit file is loaded to FPGA? And one more quick question, how to investigate state_reg of a FSM by using chipscope? Because the original name of the interesting state_reg is modified after synthesis, I dont't know which signal I should investigate now. For Altera signaltapII, it is very easy to use for on-chip debugging. And it is very easy to learn too. Miss those days when using Quartus. Thanks in advance for your input, Sics
Chipscope 9.1: Any easy way to rename and regroup signals?
Started by ●July 12, 2007
Reply by ●July 12, 20072007-07-12
On Thu, 12 Jul 2007 04:03:36 -0000, Yao Sics <yao.sics@gmail.com> wrote:>Hi Xilinx Killers, > >It is really annoying to rename and group all the signals everytime >when design is modified and new bit file is used to configure the >fpga. Anybody knows how to avoid renaming and regrouping signals in >the analyzer when new bit file is loaded to FPGA?Take a look at .cdc files (they are importd or exported from Chipscope) They contain a list of signals and aliases that you may create/edit with a text editor. Thus, you may maintain your signal list with a text editor and import it after connecting the CipScope analyzer> >And one more quick question, how to investigate state_reg of a FSM by >using chipscope? Because the original name of the interesting >state_reg is modified after synthesis, I dont't know which signal I >should investigate now.You shoulld create some intermediate signal that translates your FSM states into some binary code you may read with the ChipScope. I never found any other way, but this one works nice. Zara
Reply by ●July 12, 20072007-07-12
Hi Zara, Thank you for your input. It helps a lot. Have a nice day, Sics On Jul 12, 1:31 pm, Zara <me_z...@dea.spamcon.org> wrote:> On Thu, 12 Jul 2007 04:03:36 -0000, Yao Sics <yao.s...@gmail.com> > wrote: > > >Hi Xilinx Killers, > > >It is really annoying to rename and group all the signals everytime > >when design is modified and new bit file is used to configure the > >fpga. Anybody knows how to avoid renaming and regrouping signals in > >the analyzer when new bit file is loaded to FPGA? > > Take a look at .cdc files (they are importd or exported from > Chipscope) They contain a list of signals and aliases that you may > create/edit with a text editor. Thus, you may maintain your signal > list with a text editor and import it after connecting the CipScope > analyzer > > > > >And one more quick question, how to investigate state_reg of a FSM by > >using chipscope? Because the original name of the interesting > >state_reg is modified after synthesis, I dont't know which signal I > >should investigate now. > > You shoulld create some intermediate signal that translates your FSM > states into some binary code you may read with the ChipScope. I never > found any other way, but this one works nice. > > Zara
Reply by ●July 12, 20072007-07-12
On 2007-07-12, Zara <me_zara@dea.spamcon.org> wrote:> > Take a look at .cdc files (they are importd or exported from > Chipscope) They contain a list of signals and aliases that you may > create/edit with a text editor.But how do you name busses? Naming signals is easy... -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/
Reply by ●July 12, 20072007-07-12
Actually, to solve the problem mentioned above, before closing chipscope Analyzer save your settings it will be a .cpj extension file then when you download your new configuration file open that cpj file that you had saved. Sics On Jul 12, 1:53 pm, Ben Jackson <b...@ben.com> wrote:> On 2007-07-12, Zara <me_z...@dea.spamcon.org> wrote: > > > > > Take a look at .cdc files (they are importd or exported from > > Chipscope) They contain a list of signals and aliases that you may > > create/edit with a text editor. > > But how do you name busses? Naming signals is easy... > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/
Reply by ●July 12, 20072007-07-12
"Yao Sics" <yao.sics@gmail.com> wrote in message news:1184227210.767021.171810@57g2000hsv.googlegroups.com...> Actually, to solve the problem mentioned above, before closing > chipscope Analyzer save your settings it will be a .cpj extension file > then when you download your new configuration file open that cpj file > that you had saved. > > Sics > > >Yeah, but what a dog's breakfast that file is. If you delete busses, they persist forever in the file but with zero size. <rant follows>I'm convinced that whoever wrote chipscope never uses it on a proper heirachical design. The viewer needs to have the signal name window justified to the right, otherwise I just see the pathname of the signal I'm trying to look at. (It's not rocket science, just look at how ModelSIM does it) Come to think of it, perhaps the GUI guy comes from a place where they write from right to left? So, you can rename the signals to something shorter with either an editor on the cpj file or a lot of right-clicks. But add another bunch of signals and re-import the cdc file: all the edits disappear. Way to go, GUI writer guy. The chipscope could be so much better, with a little forethought and effort. It should be a crime to take such a good idea and hobble it like that. The underlying engine is pretty good. (But it needs a clock enable input for the clock. That would probably double it's useful frequency range) Cheers, Syms.
Reply by ●July 12, 20072007-07-12
Yao Sics <yao.sics@gmail.com> writes:> Hi Xilinx Killers, > > It is really annoying to rename and group all the signals everytime > when design is modified and new bit file is used to configure the > fpga. Anybody knows how to avoid renaming and regrouping signals in > the analyzer when new bit file is loaded to FPGA?No, it's a pain.. As Symon as pointed out, there's a bunch of flaws in the Chipscope UI.. It's only if I have to that I ever use Chipscope.> For Altera signaltapII, it is very easy to use for on-chip debugging. > And it is very easy to learn too. > Miss those days when using Quartus.Ditto. An interface done right. You can add extra signals from the waveform window and then have it recompile and get on with it. No faffing around in another separate tool. Why should I care about the chipscope core inserter? Just give me some waveforms. Grrr. Sorry, I'll stop ranting now :-) Maybe if we *all* shout loudly enough about chipscope it'll get sorted. Or Xilinx could open the protocol and at least we could write our own front end that would work properly.... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Reply by ●July 12, 20072007-07-12
On Jul 12, 12:03 am, Yao Sics <yao.s...@gmail.com> wrote:> Hi Xilinx Killers, > > It is really annoying to rename and group all the signals everytime > when design is modified and new bit file is used to configure the > fpga. Anybody knows how to avoid renaming and regrouping signals in > the analyzer when new bit file is loaded to FPGA?When adding new signals to a Chipscope project, I try to add them at the end to avoid screwing up the project. That way you can simply import your new .cdc file into your Chipscope Analyzer project and all the previous signals will stay intact (and the new signals will appear). Avoid inserting new signals by moving other signal positions around, as this will screw up the project. In order to help you setting up the Chipscope Analyzer project, take a look at csptool: http://code.google.com/p/csptool/ It's a little Perl script that regroups buses for you. Might be overkill if you have a few buses, but if you have tens, it can be very handy.> And one more quick question, how to investigate state_reg of a FSM by > usingchipscope? Because the original name of the interesting > state_reg is modified after synthesis, I dont't know which signal I > should investigate now.You can look at the synthesis report to see how XST encoded the states. Then I suggest that you create a .tok file to display the name of the state in the waveform window. Look at \ChipScope_Pro_9_1i\bin\nt \token\token_sample.tok for an example. Patrick
Reply by ●July 13, 20072007-07-13
"Patrick Dubois" <prdubois@gmail.com> wrote in message news:1184290183.837237.48920@n2g2000hse.googlegroups.com...> On Jul 12, 12:03 am, Yao Sics <yao.s...@gmail.com> wrote: >> Hi Xilinx Killers, >> >> It is really annoying to rename and group all the signals everytime >> when design is modified and new bit file is used to configure the >> fpga. Anybody knows how to avoid renaming and regrouping signals in >> the analyzer when new bit file is loaded to FPGA? > > When adding new signals to a Chipscope project, I try to add them at > the end to avoid screwing up the project. That way you can simply > import your new .cdc file into your Chipscope Analyzer project and all > the previous signals will stay intact (and the new signals will > appear). Avoid inserting new signals by moving other signal positions > around, as this will screw up the project. >Hi Patrick, So I'm still using 8.2, and this isn't the behaviour I see. An import overwrites any previous edits. Is this a new feature for 9.1?> In order to help you setting up the Chipscope Analyzer project, take a > look at csptool: > http://code.google.com/p/csptool/ >I downloaded it, sounds interesting, many thanks. All the best, Syms.
Reply by ●July 13, 20072007-07-13
On Jul 13, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote:> Hi Patrick, > So I'm still using 8.2, and this isn't the behaviour I see. An import > overwrites any previous edits. Is this a new feature for 9.1? > > > In order to help you setting up the Chipscope Analyzer project, take a > > look at csptool: > >http://code.google.com/p/csptool/ > > I downloaded it, sounds interesting, many thanks. > > All the best, Syms.I have been using Chipscope since v7 and I think that it's always been like that. After you load a new bit file, disconnect and reconnect the JTAG (JTAG chain menu). Chipscope will then discover that the number of signals changed and a dialog will pop-up asking if you want to preserve signals names (choose yes). Then you will see new unnamed signals in your signals list (they won't be in the waveform). Now you can simply import the new cdc file to retreive the name of these new signals. The rest of the Analyzer design should stay intact. Cheers, Patrick
