Hello, I require a counter which counts up on positive clock; can be reset to zero upon a reset signal; will stop counting when reached max or rollover; will restart counting only after a total reset, which is not the same as the counter reset. (2 resets) Waiting with anticipation. Thanks.
Counter ?
Started by ●July 13, 2007
Reply by ●July 13, 20072007-07-13
On 13 Jul, 11:51, <miche> wrote:> Hello, > I require a counter which counts up on positive clock; > can be reset to zero upon a reset signal; > will stop counting when reached max or rollover; > will restart counting only after a total reset, which is > not the same as the counter reset. (2 resets) > Waiting with anticipation. > Thanks.Will this do: http://tools.arantius.com/stopwatch Cheers, Jon
Reply by ●July 13, 20072007-07-13
"Jon Beniston" <jon@beniston.com> wrote in message news:1184325590.954425.86330@n2g2000hse.googlegroups.com...> On 13 Jul, 11:51, <miche> wrote: >> Hello, >> I require a counter which counts up on positive clock; >> can be reset to zero upon a reset signal; >> will stop counting when reached max or rollover; >> will restart counting only after a total reset, which is >> not the same as the counter reset. (2 resets) >> Waiting with anticipation. >> Thanks. > > Will this do: > > http://tools.arantius.com/stopwatch > > Cheers, > Jon >Hi Jon, :-) Actually that's quite a useful widget. Ta for the link! Cheers, Syms.
Reply by ●July 13, 20072007-07-13
miche wrote:> Hello, > I require a counter which counts up on positive clock; > can be reset to zero upon a reset signal; > will stop counting when reached max or rollover; > will restart counting only after a total reset, which is > not the same as the counter reset. (2 resets) > Waiting with anticipation. > Thanks. >Would you like fries with that also :-) More seriously, there are a few things you could do to demonstrate that you're not just a lazy person looking for somebody else to do your homework for you: - Are you using VHDL or Verilog or some schematic-entry tool? - Have you made any attempt yourself to implement this? - Can we see your implementation? - Do you have any simulation stimuli (testbench) to test it?
Reply by ●July 13, 20072007-07-13
> - Are you using VHDL or Verilog or some schematic-entry tool?Yes, verilo> - Have you made any attempt yourself to implement this?Yes, see my last post 2 day ago.> - Can we see your implementation?Yes, see my last post 2 day ago.> - Do you have any simulation stimuli (testbench) to test it?Yes, see my last post 2 day ago.
Reply by ●July 13, 20072007-07-13
> Hi Jon, > :-) > Actually that's quite a useful widget. Ta for the link!Miserable gits.> Cheers, Syms. > >
Reply by ●July 13, 20072007-07-13
On 13 Jul, 13:04, <miche> wrote:> > - Are you using VHDL or Verilog or some schematic-entry tool? > > Yes, verilo > > > - Have you made any attempt yourself to implement this? > > Yes, see my last post 2 day ago. > > > - Can we see your implementation? > > Yes, see my last post 2 day ago. > > > - Do you have any simulation stimuli (testbench) to test it? > > Yes, see my last post 2 day ago.I wait in anticipation for a link to your previous post 'cos I'm too lazy to search for it.
Reply by ●July 13, 20072007-07-13
On Fri, 13 Jul 2007 13:04:20 +0100, <miche> wrote: repeat(3)>Yes, see my last post 2 day ago.; Why should anyone *except you* waste time trawling through a NG looking for posts by you, when you can't be bothered to include either a reference or the germane content in your question? Contrary to what appears to be your opinion, the world does not owe you a living, but only a fair hearing. You'll get that soon enough if you make a fair attempt to be heard. I could write a solution to your counter problem in considerably less time than it's taken me to write this, but I don't really see the point. Looks like plenty of other people feel pretty much the same way. At least two of the people who replied to this thread have a spectacularly impressive history of pertinent, courteous and expert responses to various questions. The balance of evidence is that it's not *their* fault that you're dissatisfied. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●July 13, 20072007-07-13
Jon Beniston (jon@beniston.com) wrote: : On 13 Jul, 11:51, <miche> wrote: : > Hello, : > I require a counter which counts up on positive clock; : > can be reset to zero upon a reset signal; : > will stop counting when reached max or rollover; : > will restart counting only after a total reset, which is : > not the same as the counter reset. (2 resets) : > Waiting with anticipation. : > Thanks. : Will this do: : http://tools.arantius.com/stopwatch : Cheers, : Jon Jon that only has one reset - the OP clearly mentioned that 2 are required... :) Cheers, Chris
Reply by ●July 13, 20072007-07-13
miche wrote:> Hello, > I require a counter which counts up on positive clock; > can be reset to zero upon a reset signal; > will stop counting when reached max or rollover; > will restart counting only after a total reset, which is > not the same as the counter reset. (2 resets) > Waiting with anticipation. > Thanks.If you were to write the function in C code, what would it look like? I'm hoping you have the software background. You're working with CPLDs which isn't the typical homework assignment thing. Are you taking your first steps into programmable logic? Are you a hobbyist, electrical engineer, student, or software guy? Knowing this can help us shape our response. And please start asking questions rather than telling us something and waiting. - John_H
