Generating video noise.

I want to program an FPGA to generate two-dimensional,
10-bit video white noise. Any suggestions? I'm not sure if an
independent LFSR per bit would work. If so, would I want
different lengths per bit, or would I just initialize the different
bits at different times?

Thanks.

Pete 

I spend most of my day trying to minimize dark noise and you're looking to 
add white noise.  Sorry for the useless post, but this struck me as funny. 
Out of curiosity, what is the application?

"Pete Fraser" <pfraser@covad.net> wrote in message 
news:139qo03ef5pigbb@news.supernews.com...
>I want to program an FPGA to generate two-dimensional,
> 10-bit video white noise. Any suggestions? I'm not sure if an
> independent LFSR per bit would work. If so, would I want
> different lengths per bit, or would I just initialize the different
> bits at different times?
>
> Thanks.
>
> Pete
> 

"Pete Fraser" <pfraser@covad.net> writes:
> I want to program an FPGA to generate two-dimensional,
> 10-bit video white noise. Any suggestions? I'm not sure if an
> independent LFSR per bit would work.  If so, would I want
> different lengths per bit,

If they're running on the same clock, you are likely to see an
obvious pattern to the bits, especially if they are the same length
LFSRs.

If you are using an FPGA that has hardware multipliers (as most do
nowdays), I'd suggest using a linear congruential generator:

    http://en.wikipedia.org/wiki/Linear_congruential_generator

What you want to avoid is a modulus that isn't a power of two.  The
first set of coefficients listed in the "Example LCGs" section uses
a modulus of 2^32.  It generates a 32-bit pseudo-random number for
each multiply, so you could get three 10-bit video samples per
iteration.

In typical Xilinx FPGAs, you get 18-bit signed multipliers, so
you would build a 32-bit unsigned multiplier from four of those and
some adders.  Maybe the tools can infer that from a Verilog or VHDL
multiplication operator, or maybe you can use Coregen.

If your data rate requirement isn't too high, you can implement
the 32-bit multiplier using a single hardware multiplier cycled
four times.

It is possible that an LCG will still result in too much pattern
for your application.  If so, it is possible to implement the
Mersenne Twister in hardware.  While it is not suitable as a
source of pseudorandom sequences for cryptography, it has a long
enough period (approx. 10^600) that it should be suitable as a general
noise source.

Eric

Eric Smith wrote:

> If they're running on the same clock, you are likely to see an
> obvious pattern to the bits, especially if they are the same length
> LFSRs.

What if their periods are all relatively prime?

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

"Pete Fraser" <pfraser@covad.net> wrote in message 
news:139qo03ef5pigbb@news.supernews.com...
>I want to program an FPGA to generate two-dimensional,
> 10-bit video white noise. Any suggestions? I'm not sure if an
> independent LFSR per bit would work. If so, would I want
> different lengths per bit, or would I just initialize the different
> bits at different times?
>
> Thanks.
>
> Pete


Use a 64 bit PRNG and randomly pick out the bits. I have used this in the 
past on a video generator using 12 bit video with great success with 
absolutely  no visible repeat patterning.

http://img.villagephotos.com/p/2007-7/1268869/prng64.jpg

Icky 

"Icky Thwacket" <it@it.it> wrote in message 
news:469dc3ea$0$1609$ed2619ec@ptn-nntp-reader02.plus.net...
>
> "Pete Fraser" <pfraser@covad.net> wrote in message 
> news:139qo03ef5pigbb@news.supernews.com...
>>I want to program an FPGA to generate two-dimensional,
>> 10-bit video white noise. Any suggestions? I'm not sure if an
>> independent LFSR per bit would work. If so, would I want
>> different lengths per bit, or would I just initialize the different
>> bits at different times?
>>
>> Thanks.
>>
>> Pete
>
>
> Use a 64 bit PRNG and randomly pick out the bits. I have used this in the 
> past on a video generator using 12 bit video with great success with 
> absolutely  no visible repeat patterning.
>
> http://img.villagephotos.com/p/2007-7/1268869/prng64.jpg
>
> Icky
OOOps - sorry its actually a 32 bit PRNG with a 32 bit extension used for 
increased bit spacing for better randomization when generating a multibit 
video level. 

"Eric Smith" <eric@brouhaha.com> wrote in message 
news:qh8x9efr5b.fsf@ruckus.brouhaha.com...
> "Pete Fraser" <pfraser@covad.net> writes:
>> I want to program an FPGA to generate two-dimensional,
>> 10-bit video white noise. Any suggestions? I'm not sure if an
>> independent LFSR per bit would work.  If so, would I want
>> different lengths per bit,
..snip
>
> It is possible that an LCG will still result in too much pattern
> for your application.  If so, it is possible to implement the
> Mersenne Twister in hardware.

I have one on my website if you need an example,

http://www.ht-lab.com/freecores/mt32/mersenne.html

Hans
www.ht-lab.com


While it is not suitable as a
> source of pseudorandom sequences for cryptography, it has a long
> enough period (approx. 10^600) that it should be suitable as a general
> noise source.
>
> Eric 

Pete Fraser wrote:
> I want to program an FPGA to generate two-dimensional,
> 10-bit video white noise. Any suggestions? I'm not sure if an
> independent LFSR per bit would work. If so, would I want
> different lengths per bit, or would I just initialize the different
> bits at different times?
> 
> Thanks.
> 
> Pete 
> 
> 
You can use an LFSR but use one that skips ten steps forward in the 
sequence on each cycle so that the lower ten bits are not correlated 
from cycle to cycle.  If you used, for example, a 17-bit LFSR, you would 
cycle through all 2^17-1 sequences, since 2^17-1 mod 10 = 1.  If that 
makes sense.  I forget what this kind of LFSR is called, but they are 
easy to make, because you can usually write a double loop in HDL and a 
good synthesizer like Synplify will take care of the rest.  -Kevin

I wrote:
> If they're running on the same clock, you are likely to see an
> obvious pattern to the bits, especially if they are the same length
> LFSRs.

Mark McDougall wrote:
> What if their periods are all relatively prime?

That will certainly help.  Perhaps that will be satisfactory; I'm not
really sure.  Worth a try.

"HT-Lab" <hans64@ht-lab.com> wrote in message 
news:Z8kni.12$SI5.4@newsfe2-gui.ntli.net...

> I have [a Mersenne Twister] on my website if you need an example,
>
> http://www.ht-lab.com/freecores/mt32/mersenne.html

Thanks.

That worked beautifully.
I felt guilty destroying the histogram by limiting or scaling
the range to 601 limits, but it's fine for my purposes.

The original paper is a bit beyond me, but I couldn't
see any obvious way to restrict the number range.

Once again, thanks.

Pete