Greetings, all, I have read through many postings about bypass/decoupling capacitors for Xilinx FPGAs at comp.arch.fpga. It seems to me common "solution" (there are many, I'm sure) to use at most 10 or 20 caps for the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF capacitor, 0603 package, perhaps). I guess I just want a quick a dirty suggestion of what best to do (in terms of bypass caps) for this board. It's goal is to be a small board (current size is 2 by 5 inches or less) and only has the most basic components: two SRAM modules, an EEPROM module, power regulation via a TPS75003, an oscillator, and a few miscellaneous components (LEDs, etc.) with the rest of the free pins on the Spartan 3 (PQ208 package) becoming User I/O pins. The goal is to be as small as possible, and the board will be used by students (like myself) on projects as an alternative to a microprocessor solution (though the Spartan-3 will likely be configured with Microblaze). Also, right now I'm limiting myself to just four layers, with the one inner layer as a GROUND plane and the other as a VCCO plane. I doubt we'll use the board for really high- speed projects (in the gigahertz range...), but regardless I still have doubts as to what caps to use. I know there are many, many postings of similar topics as this one but I just need confirmation that I can "get away" with using as few bypass caps as possible. There are discussions relating to more advanced electrical concepts that I do not fully understand, and some real-world experience and recommendation concerning my board setup and chip selection would be greatly appreciated. Thanks. Lue Her University of St. Thomas (St. Paul, MN)
Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
Started by ●July 18, 2007
Reply by ●July 18, 20072007-07-18
<Lue.Her@gmail.com> wrote in message news:1184776967.209392.21280@j4g2000prf.googlegroups.com...> Greetings, all, > > I have read through many postings about bypass/decoupling capacitors > for Xilinx FPGAs at comp.arch.fpga. It seems to me common > "solution" (there are many, I'm sure) to use at most 10 or 20 caps for > the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF > capacitor, 0603 package, perhaps). I guess I just want a quick a dirty > suggestion of what best to do (in terms of bypass caps) for this > board. It's goal is to be a small board (current size is 2 by 5 inches > or less) and only has the most basic components: two SRAM modules, an > EEPROM module, power regulation via a TPS75003, an oscillator, and a > few miscellaneous components (LEDs, etc.) with the rest of the free > pins on the Spartan 3 (PQ208 package) becoming User I/O pins. >Hi Her, One cap for each power pin is gonna be about as good as you can do with the PQ208 package. In fact, the package is bad enough so that you can probably share bypass caps between two power pins and it wouldn't degrade much further. Do yourself a favour and use a FBGA instead, the SI performance is a great deal better. (You can rework them with a toaster oven, apparently!) HTH., Syms.
Reply by ●July 18, 20072007-07-18
Lue Her, A student platform or educational project should first of all be robust: you have no idea how clever they are, and they will do all kinds of wonderful things that you did not think possible (I know, as I helped design the UC Berkeley FPGA CS150 pcb). I have also seen the Standford lab pcb, San Jose State University pcb, Digilent pcb's, etc etc etc etc... Every thing you have mentioned in your post will lead to certain failure, and disappointment. If you want to cut corners, go with someone besides Xilinx: I do not want to have bad things said about Xilinx! Limiting layers, limiting bypass, are all things that you might do if you are Samsung/Sony/LG, and the application is fixed and unchanging (a LCD TV). These are all things you would not do for a general purpose platform, intended to perform a wide range of intended applications. Rather, follow our user's guides to the letter, and be successful. Austin
Reply by ●July 18, 20072007-07-18
Lue.Her@gmail.com wrote:>Greetings, all, > >I have read through many postings about bypass/decoupling capacitors >for Xilinx FPGAs at comp.arch.fpga. It seems to me common >"solution" (there are many, I'm sure) to use at most 10 or 20 caps for >the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF >capacitor, 0603 package, perhaps). I guess I just want a quick a dirtyBypassing each power pin with a 0402 10nf and a 0402 100nf capacitor is a good start. Connect the capacitor directly to the power supply pin and use 2 via's to ground for each capacitor. Place a 10uf MLCC capacitor for each supply close to the fpga for bulk decoupling. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl
Reply by ●July 18, 20072007-07-18
"Nico Coesel" <nico@puntnl.niks> wrote in message news:469e6836.831123642@news.planet.nl...> Lue.Her@gmail.com wrote: > >>Greetings, all, >> >>I have read through many postings about bypass/decoupling capacitors >>for Xilinx FPGAs at comp.arch.fpga. It seems to me common >>"solution" (there are many, I'm sure) to use at most 10 or 20 caps for >>the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF >>capacitor, 0603 package, perhaps). I guess I just want a quick a dirty > > Bypassing each power pin with a 0402 10nf and a 0402 100nf capacitor > is a good start. Connect the capacitor directly to the power supply > pin and use 2 via's to ground for each capacitor. Place a 10uf MLCC > capacitor for each supply close to the fpga for bulk decoupling. >Hi Nico, I'd be interested to hear your reasoning as to why you would use two capacitors for each pin, especially bearing in mind this is a PQ208 package. Do you own Murata shares by any chance? ;-) Also, why would you use two different values? Thanks, Syms.
Reply by ●July 18, 20072007-07-18
On Wed, 18 Jul 2007 09:42:47 -0700, Lue.Her@gmail.com wrote:>Greetings, all, > >I have read through many postings about bypass/decoupling capacitors >for Xilinx FPGAs at comp.arch.fpga. It seems to me common >"solution" (there are many, I'm sure) to use at most 10 or 20 caps for >the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF >capacitor, 0603 package, perhaps). I guess I just want a quick a dirty >suggestion of what best to do (in terms of bypass caps) for this >board. It's goal is to be a small board (current size is 2 by 5 inches >or less) and only has the most basic components: two SRAM modules, an >EEPROM module, power regulation via a TPS75003, an oscillator, and a >few miscellaneous components (LEDs, etc.) with the rest of the free >pins on the Spartan 3 (PQ208 package) becoming User I/O pins. > >The goal is to be as small as possible, and the board will be used by >students (like myself) on projects as an alternative to a >microprocessor solution (though the Spartan-3 will likely be >configured with Microblaze). Also, right now I'm limiting myself to >just four layers, with the one inner layer as a GROUND plane and the >other as a VCCO plane. I doubt we'll use the board for really high- >speed projects (in the gigahertz range...), but regardless I still >have doubts as to what caps to use. > >I know there are many, many postings of similar topics as this one but >I just need confirmation that I can "get away" with using as few >bypass caps as possible. There are discussions relating to more >advanced electrical concepts that I do not fully understand, and some >real-world experience and recommendation concerning my board setup and >chip selection would be greatly appreciated. > >Thanks. >Lue Her >University of St. Thomas (St. Paul, MN)6 layers would make life a lot easier, one ground plane and two power planes. One power plane can be 3.3 volts, and the other can be split 2.5 and 1.2, one island inside the FPGA and a big pour outside. That leaves three signal layers, and you can route signals on the 2.5/1.2 layer too, once you make the FPGA happy. Two more layers won't cost much more. We ususlly use 4 caps per supply per FPGA, 0.33 uF 0603. Never had a problem, even in systems where we measure jitter in picoseconds. Use more if it makes you feel better, but they won't change anything. For fun, lay out a board with more caps and depopulate it until something malfunctions. Write a paper. John
Reply by ●July 19, 20072007-07-19
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:vvet935t6s89tn6pkqo9m220mdl52ccnnt@4ax.com...> On Wed, 18 Jul 2007 09:42:47 -0700, Lue.Her@gmail.com wrote: > > > 6 layers would make life a lot easier, one ground plane and two power > planes. One power plane can be 3.3 volts, and the other can be split > 2.5 and 1.2, one island inside the FPGA and a big pour outside. That > leaves three signal layers, and you can route signals on the 2.5/1.2 > layer too, once you make the FPGA happy. Two more layers won't cost > much more. >Hi John, If I had six layers, I'd make 2 and 5 ground planes. Then when signals via from one side to the other, their impedance to the ground plane stays pretty much the same, provided you use a ground via near to the signal via. This is also true of LVDS pairs, as the P and N signals are usually poorly coupled to each other, but strongly coupled to ground. Route the powers on one of layer 3 or 4.> > We ususlly use 4 caps per supply per FPGA, 0.33 uF 0603. Never had a > problem, even in systems where we measure jitter in picoseconds. Use > more if it makes you feel better, but they won't change anything. > > For fun, lay out a board with more caps and depopulate it until > something malfunctions. Write a paper. > > John >Right, it's hard to get bypassing wrong. If you cover the board in bypass caps it'll work just fine, but it'll cost you. Beware, the via holes you have to drill to connect them can be more expensive than the parts. I would suspect that in a 'real' system, the removal of bypass caps will probably cause some analog part of the board to fail before the FPGA. The switching noise from the FPGA can spread back through the power network more easily as bypassing is reduced. Cheers, Syms.
Reply by ●July 19, 20072007-07-19
> Right, it's hard to get bypassing wrong. If you cover the board in byp=ass> caps it'll work just fine, but it'll cost you. Beware, the via holes y=ou> have to drill to connect them can be more expensive than the parts. > I would suspect that in a 'real' system, the removal of bypass caps wi=ll> probably cause some analog part of the board to fail before the FPGA. =The> switching noise from the FPGA can spread back through the power networ=k => more > easily as bypassing is reduced. > Cheers, Syms.Hm, I'm wondering about something... Someone talked about vias and caps and being careful about not "slottin= g = the ground plane"... what does this mean ? (or was it slitting ?) Was it this : http://home.peufeu.com/nik/fpga/board_v03/slit.png (top =3D bad, bottom =3D good) ? (I try to leave enough space between my vias so that the copper pour = can... well, pour itself). Or does it mean something else ? Also, well, on my FPGA each power pin has its own decoupling cap on the= = bottom of the PCB below the FPGA, each cap has + and GND connected to th= e = appropriate planes with vias. Question : I can also connect all the caps in parallel using traces. Is= = this harmful, good, or useless ? Like this : http://home.peufeu.com/nik/fpga/board_v03/decoupling.png Top : caps' GND connected to the plane by vias + paralleled using a tra= ce Bottom : caps' GND only connected through vias to the plane PS: I checked ; I can't use BGA packages because the min via = restring/drill of the PCB fab I plan to use is too large. But it's not = that expensive and the PCBs are electrically tested... Thanks ;)
Reply by ●July 19, 20072007-07-19
Hi, Sorry, I can't quote your reply properly, bloody opera, I guess! Anyway, yes top bad. If a signal came on the top level from north-east to the centre via, and left on the bottom layer to the south-west, the return current has to travel around the slot cut by the 5 vias. If you can flow the cu in between the vias, that's better. As for connecting the caps together, it might help. Personally I've long given up using planes for power. I route the power to the device and use copper pours at the part. This works well. Using puddles to connect the caps can be a help, I think we mentioned this in a thread a while back about X2Y caps. Google will find it. However, as you're stuck with the PQ208 package, it probably will make no difference. The lead frame has such high inductance, so the bypass caps don't have the desired benefit at the die. Doubling up the ground vias probably makes sense. BTW., putting the caps on the same side as the IC get's rid of the via inductance problem, but probably will screw with your signal routing. However, what you've shown looks like it'll work fine. HTH., Syms.
Reply by ●July 19, 20072007-07-19
On Thu, 19 Jul 2007 11:22:52 +0100, "Symon" <symon_brewer@hotmail.com> wrote:>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:vvet935t6s89tn6pkqo9m220mdl52ccnnt@4ax.com... >> On Wed, 18 Jul 2007 09:42:47 -0700, Lue.Her@gmail.com wrote: >> >> >> 6 layers would make life a lot easier, one ground plane and two power >> planes. One power plane can be 3.3 volts, and the other can be split >> 2.5 and 1.2, one island inside the FPGA and a big pour outside. That >> leaves three signal layers, and you can route signals on the 2.5/1.2 >> layer too, once you make the FPGA happy. Two more layers won't cost >> much more. >> >Hi John, >If I had six layers, I'd make 2 and 5 ground planes.That's a lot to give up. We use one ground plane, between the power planes, maybe 3=power, 4=gnd, 5=power. Long traces would run on 2 and 6, and layer 1 has parts and short traces. Trace impedances would vary a bit between all three routing layers, so trace widths can be average-compromised, or tuned per layer when it really matters. We often cheat and run some short traces on the power plane layers, "slitting" the plane, and that works fine too. Even ground, sometimes. We'll also occasionally slit planes as thermal insulators, to keep temperature gradients away from tender stuff.>Then when signals via >from one side to the other, their impedance to the ground plane stays pretty >much the same, provided you use a ground via near to the signal via.We don't believe in the "return current" dogma that's so popular these days. The three planes are so tightly coupled by plane-plane capacitance you can assume them to be equipotential, like a solid block of copper. TDR testing confirms.> This is >also true of LVDS pairs, as the P and N signals are usually poorly coupled >to each other, but strongly coupled to ground. Route the powers on one of >layer 3 or 4.Planes themselves are the best bypass caps, so we try to not "route" power, but pour it.>> >> We ususlly use 4 caps per supply per FPGA, 0.33 uF 0603. Never had a >> problem, even in systems where we measure jitter in picoseconds. Use >> more if it makes you feel better, but they won't change anything. >> >> For fun, lay out a board with more caps and depopulate it until >> something malfunctions. Write a paper. >> >> John >> >Right, it's hard to get bypassing wrong.Which is why so many people have such different opinions, and why the looniest signal-integrity consultants are always right.>If you cover the board in bypass >caps it'll work just fine, but it'll cost you. Beware, the via holes you >have to drill to connect them can be more expensive than the parts. >I would suspect that in a 'real' system, the removal of bypass caps will >probably cause some analog part of the board to fail before the FPGA. The >switching noise from the FPGA can spread back through the power network more >easily as bypassing is reduced.I know one guy who doesn't use bypass caps at all, and his boards work too. Grounding and bypassing are easy. We've had a lot more trouble lately with clock integrity, as the fpga clock inputs get faster and faster and more sensitive to edge noise. Even CCLK. We've been putting tiny logic schmitts adjacent to clock and CCLK pins. LVDS clocks are ok, but routing is harder and even small routing asymetries can make for nasties. As you say, a diff pair on a multilayer board behaves more like two independent signals. John
