Problem with X_FF primitive acting as a latch instead of a fliflop

Hi alls,

I've a amazing problem in my virtex XC2V1000 design.

I've verilog code which normaly should generate a D flipFlop with
preload ( and it did in functional simulation):
input [7:0] reset;
input [7:0] n_set;
input [7:0] d;
input clockIn;
output [7:0] out;

reg [7:0] out_reg;
wire [7:0] out = out_reg;
wire trigSig = |(reset | ~(n_set));
always@(posedge clockIn or posedge trigSig)
begin
     if(trigSig)
         out_reg = ~reset;
     else
         out_reg = d;
end

The problem append when I use post translate simulation model ( based
on simprims ) after synthesize my design with ISE 9.1i
It seems my Flipflop has been convert to a latch : out_reg copy the d
value during clockIn high state and block it during low state.
So I verify which primitive was instantiate in the post translate
simulation model generated by ISE, and I found a X_FF which is a
flipflop... So I don't understand anything.. It looks very strange.. :-
(

For information, I simulate with Cadence NC-verilog and NC-sim and I
join simprims directory to my project to have Xilinx primitives.

If anyone could help me, because I haven't more ideas about what
append..

Thanks by advance, best regards, Michel Talon.

Check the signal integrity of your clock. You may have double edges.

Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter)
and observe its behavior. It will clearly indicate any double-
triggering.
Peter Alfke, from home.
==================
On Jul 26, 8:09 am, michel.ta...@gmail.com wrote:
> Hi alls,
>
> I've a amazing problem in my virtex XC2V1000 design.
>
> I've verilog code which normaly should generate a D flipFlop with
> preload ( and it did in functional simulation):
> input [7:0] reset;
> input [7:0] n_set;
> input [7:0] d;
> input clockIn;
> output [7:0] out;
>
> reg [7:0] out_reg;
> wire [7:0] out = out_reg;
> wire trigSig = |(reset | ~(n_set));
> always@(posedge clockIn or posedge trigSig)
> begin
>      if(trigSig)
>          out_reg = ~reset;
>      else
>          out_reg = d;
> end
>
> The problem append when I use post translate simulation model ( based
> on simprims ) after synthesize my design with ISE 9.1i
> It seems my Flipflop has been convert to a latch : out_reg copy the d
> value during clockIn high state and block it during low state.
> So I verify which primitive was instantiate in the post translate
> simulation model generated by ISE, and I found a X_FF which is a
> flipflop... So I don't understand anything.. It looks very strange.. :-
> (
>
> For information, I simulate with Cadence NC-verilog and NC-sim and I
> join simprims directory to my project to have Xilinx primitives.
>
> If anyone could help me, because I haven't more ideas about what
> append..
>
> Thanks by advance, best regards, Michel Talon.

I've checked my clock on the waveform viewer and it seems good..
but I did what you say, I add a divisor on my clock, and I send
divided clock to my process. ISE is running, so I'm going to see the
results in ten minutes.. ( because the rest of the design is big, and
it's too long to synthesize.. )

thanks


On 26 juil, 17:18, Peter Alfke <al...@sbcglobal.net> wrote:
> Check the signal integrity of your clock. You may have double edges.
>
> Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter)
> and observe its behavior. It will clearly indicate any double-
> triggering.
> Peter Alfke, from home.
> ==================
> On Jul 26, 8:09 am, michel.ta...@gmail.com wrote:
>
> > Hi alls,
>
> > I've a amazing problem in my virtex XC2V1000 design.
>
> > I've verilog code which normaly should generate a D flipFlop with
> > preload ( and it did in functional simulation):
> > input [7:0] reset;
> > input [7:0] n_set;
> > input [7:0] d;
> > input clockIn;
> > output [7:0] out;
>
> > reg [7:0] out_reg;
> > wire [7:0] out = out_reg;
> > wire trigSig = |(reset | ~(n_set));
> > always@(posedge clockIn or posedge trigSig)
> > begin
> >      if(trigSig)
> >          out_reg = ~reset;
> >      else
> >          out_reg = d;
> > end
>
> > The problem append when I use post translate simulation model ( based
> > on simprims ) after synthesize my design with ISE 9.1i
> > It seems my Flipflop has been convert to a latch : out_reg copy the d
> > value during clockIn high state and block it during low state.
> > So I verify which primitive was instantiate in the post translate
> > simulation model generated by ISE, and I found a X_FF which is a
> > flipflop... So I don't understand anything.. It looks very strange.. :-
> > (
>
> > For information, I simulate with Cadence NC-verilog and NC-sim and I
> > join simprims directory to my project to have Xilinx primitives.
>
> > If anyone could help me, because I haven't more ideas about what
> > append..
>
> > Thanks by advance, best regards, Michel Talon.

Are you *certian* you're looking at the flop output in the simulation and 
not accidentally an internal signal?

[By the way - the "I've" contraction is commonly used for verbs such as 
"I've checked" but I've only seen (I've... seen) the use with nouns (e.g., 
I've a problem) with posts from India.  It's distracting whenever I see 
"I've a noun" constructs.  You still communicate, it just takes away from 
your message.]



<michel.talon@gmail.com> wrote in message 
news:1185462599.540368.277580@g4g2000hsf.googlegroups.com...
> Hi alls,
>
> I've a amazing problem in my virtex XC2V1000 design.
>
> I've verilog code which normaly should generate a D flipFlop with
> preload ( and it did in functional simulation):
> input [7:0] reset;
> input [7:0] n_set;
> input [7:0] d;
> input clockIn;
> output [7:0] out;
>
> reg [7:0] out_reg;
> wire [7:0] out = out_reg;
> wire trigSig = |(reset | ~(n_set));
> always@(posedge clockIn or posedge trigSig)
> begin
>     if(trigSig)
>         out_reg = ~reset;
>     else
>         out_reg = d;
> end
>
> The problem append when I use post translate simulation model ( based
> on simprims ) after synthesize my design with ISE 9.1i
> It seems my Flipflop has been convert to a latch : out_reg copy the d
> value during clockIn high state and block it during low state.
> So I verify which primitive was instantiate in the post translate
> simulation model generated by ISE, and I found a X_FF which is a
> flipflop... So I don't understand anything.. It looks very strange.. :-
> (
>
> For information, I simulate with Cadence NC-verilog and NC-sim and I
> join simprims directory to my project to have Xilinx primitives.
>
> If anyone could help me, because I haven't more ideas about what
> append..
>
> Thanks by advance, best regards, Michel Talon. 

On 26 juil, 17:18, Peter Alfke <al...@sbcglobal.net> wrote:
> Check the signal integrity of your clock. You may have double edges.
>
> Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter)
> and observe its behavior. It will clearly indicate any double-
> triggering.
> Peter Alfke, from home.
> ==================

You are right, by dividing my clock by 2, I divide by 2 out_reg value
variations.. but I don't understand why my clock is like that, because
when I look it one level up, it is fine. And I see something strange
on the divided clock, it's like that :
________        __   ________________               ____    _
|             |____|   |_|                            |________|      |
__| |
instead of the expected clock :
________________                             ________________
|                           |
________________|
divided by 2 :
________               ________
|             |________|             |________

There is a ratio by 2 : High state = 8x, Low state = 4x, High state =
2x, Low state = 1x..

On 26 juil, 17:56, "John_H" <newsgr...@johnhandwork.com> wrote:
> Are you *certian* you're looking at the flop output in the simulation and
> not accidentally an internal signal?
>
Yes I think, because I use the synthesis keep attribute to keep the
signal name during synthesis.

> [By the way - the "I've" contraction is commonly used for verbs such as
> "I've checked" but I've only seen (I've... seen) the use with nouns (e.g.,
> I've a problem) with posts from India.  It's distracting whenever I see
> "I've a noun" constructs.  You still communicate, it just takes away from
> your message.]

Thank you for the explanation, my english is not very fine... :-(

> I've verilog code which normaly should generate a D flipFlop with
> preload ( and it did in functional simulation):

> always@(posedge clockIn or posedge trigSig)
> begin
>      if(trigSig)
>          out_reg =3D ~reset;
>      else
>          out_reg =3D d;
> end

	Replace "=3D" with "<=3D".

I suppose you have reflections on your clock input. Your scope may not
be fast enough to see these reflections of perhaps 1 to 3 ns duration.
There are several ways to solve this, depending on the internal clock
distribution, depending on your willingness to change the pc-board,
whether this is a one-off or a production design, etc.
But when you see a single toggle flip-flop misbehaving, you know that
you have to do something.
Peter Alfke, Xilinx Applications

On Jul 26, 9:54 am, michel.ta...@gmail.com wrote:
> On 26 juil, 17:18, Peter Alfke <al...@sbcglobal.net> wrote:
>
> > Check the signal integrity of your clock. You may have double edges.
>
> > Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter)
> > and observe its behavior. It will clearly indicate any double-
> > triggering.
> > Peter Alfke, from home.
> > ==================
>
> You are right, by dividing my clock by 2, I divide by 2 out_reg value
> variations.. but I don't understand why my clock is like that, because
> when I look it one level up, it is fine. And I see something strange
> on the divided clock, it's like that :
> ________        __   ________________               ____    _
> |             |____|   |_|                            |________|      |
> __| |
> instead of the expected clock :
> ________________                             ________________
> |                           |
> ________________|
> divided by 2 :
> ________               ________
> |             |________|             |________
>
> There is a ratio by 2 : High state = 8x, Low state = 4x, High state =
> 2x, Low state = 1x..
>
> On 26 juil, 17:56, "John_H" <newsgr...@johnhandwork.com> wrote:> Are you *certian* you're looking at the flop output in the simulation and
> > not accidentally an internal signal?
>
> Yes I think, because I use the synthesis keep attribute to keep the
> signal name during synthesis.
>
> > [By the way - the "I've" contraction is commonly used for verbs such as
> > "I've checked" but I've only seen (I've... seen) the use with nouns (e.g.,
> > I've a problem) with posts from India.  It's distracting whenever I see
> > "I've a noun" constructs.  You still communicate, it just takes away from
> > your message.]
>
> Thank you for the explanation, my english is not very fine... :-(

Peter Alfke wrote:

> I suppose you have reflections on your clock input. Your scope may not
> be fast enough to see these reflections of perhaps 1 to 3 ns duration.
> There are several ways to solve this, depending on the internal clock
> distribution, depending on your willingness to change the pc-board,
> whether this is a one-off or a production design, etc.
> But when you see a single toggle flip-flop misbehaving, you know that
> you have to do something.
> Peter Alfke, Xilinx Applications

I'm not sure he is at the silicon yet - I think this is still
a simulation result ?
OP:
> The problem append when I use post translate simulation model ( based
> on simprims ) after synthesize my design with ISE 9.1i
> It seems my Flipflop has been convert to a latch : out_reg copy the d
> value during clockIn high state and block it during low state.
> So I verify which primitive was instantiate in the post translate
> simulation model generated by ISE, and I found a X_FF which is a
> flipflop... So I don't understand anything.. It looks very strange.. :-

michel.talon@gmail.com wrote:
> Hi alls,
> 
> I've a amazing problem in my virtex XC2V1000 design.
> 
> I've verilog code which normaly should generate a D flipFlop with
> preload ( and it did in functional simulation):
> input [7:0] reset;
> input [7:0] n_set;
> input [7:0] d;
> input clockIn;
> output [7:0] out;
> 
> reg [7:0] out_reg;
> wire [7:0] out = out_reg;
> wire trigSig = |(reset | ~(n_set));
> always@(posedge clockIn or posedge trigSig)
> begin
>      if(trigSig)
>          out_reg = ~reset;
>      else
>          out_reg = d;
> end

I don't know the Virtex 2, but how on a virtex 4 I don't
see how to implement that ... (unless reset is constant).

But I may be missing something ...


	Sylvain

Hi,
First, thanks a lot,  you was right..

In fact, i don't use scope for the moment, I simulate only post
translate simulation model.
But what you said was verified, I've looked about my clock generation,
and it comes from combinatorial logical block.
So I decided to reclock my clock with a faster clock ( fast clock =
50MHz , my clock = 2 MHz ) to it prevent from glitchs.
And it works fine ! Problems disappeared..

But, there is something I don't understand, why can I not seen the
glitchs on the clock on my waveform viewer ? I simulate with a time
unit of 100ps, and the clock seems to be clean.. Is it due to a
simulator option ?

thanks




On 26 juil, 19:50, Peter Alfke <pe...@xilinx.com> wrote:
> I suppose you have reflections on your clock input. Your scope may not
> be fast enough to see these reflections of perhaps 1 to 3 ns duration.
> There are several ways to solve this, depending on the internal clock
> distribution, depending on your willingness to change the pc-board,
> whether this is a one-off or a production design, etc.
> But when you see a single toggle flip-flop misbehaving, you know that
> you have to do something.
> Peter Alfke, Xilinx Applications