Best CPU platform(s) for FPGA synthesis

"Wei Wang" <camwwang@gmail.com> wrote in message 
news:1186091680.680639.251840@z24g2000prh.googlegroups.com...
> Found similar memory recommendations for Xilinx's largest XC5VLX330
> FPGA,
> http://www.xilinx.com/ise/products/memory.htm#v5lx
> only Linux-64 machines are supported, memory recommendation: typical
> 7.2GB and peak 10.6GB.

This web page needs to be updated: NT64 is also supported, but runtime
will be faster on Linux64, so that's what we recommend.

Steve 

Hi Steve,

Could you give us (Xilinx users) some more detailed recommendations on what 
would be the best platform to run ISE/EDK tools when working on midsize to 
big designs? Tell us what you are using @ Xilinx? :)



Thanks,
/Mikhail




<steve.lass@xilinx.com> wrote in message news:f8tksu$caa1@cnn.xilinx.com...
> "Wei Wang" <camwwang@gmail.com> wrote in message 
> news:1186091680.680639.251840@z24g2000prh.googlegroups.com...
>> Found similar memory recommendations for Xilinx's largest XC5VLX330
>> FPGA,
>> http://www.xilinx.com/ise/products/memory.htm#v5lx
>> only Linux-64 machines are supported, memory recommendation: typical
>> 7.2GB and peak 10.6GB.
>
> This web page needs to be updated: NT64 is also supported, but runtime
> will be faster on Linux64, so that's what we recommend.
>
> Steve
> 

I can give you some general recommendations. For the best place and route 
runtimes,
use a 64bit Linux system. If your design is small enough to fit into 4G of 
memory
(LX110 or smaller), and you are not programming devices (the 32bit cable 
drivers
don't work on a 64bit system), you can use the 32bit executables to save 
memory.
Otherwise, go ahead and use the 64bit executables. They use more memory and
the runtime is simular.

As mentioned earlier, synthesis, map, place and route do not use 
multithreading, so
you will not get an advantage using multiple processors for a single design. 
However,
ProjNav is multithreaded so if you are doing different tasks, other 
processors will
be used. In addition, upcoming software releases will use those processors.

Steve

"MM" <mbmsv@yahoo.com> wrote in message 
news:5hf8n2F3k0uqkU1@mid.individual.net...
> Hi Steve,
>
> Could you give us (Xilinx users) some more detailed recommendations on 
> what would be the best platform to run ISE/EDK tools when working on 
> midsize to big designs? Tell us what you are using @ Xilinx? :)
>
>
>
> Thanks,
> /Mikhail
>
>
>
>
> <steve.lass@xilinx.com> wrote in message 
> news:f8tksu$caa1@cnn.xilinx.com...
>> "Wei Wang" <camwwang@gmail.com> wrote in message 
>> news:1186091680.680639.251840@z24g2000prh.googlegroups.com...
>>> Found similar memory recommendations for Xilinx's largest XC5VLX330
>>> FPGA,
>>> http://www.xilinx.com/ise/products/memory.htm#v5lx
>>> only Linux-64 machines are supported, memory recommendation: typical
>>> 7.2GB and peak 10.6GB.
>>
>> This web page needs to be updated: NT64 is also supported, but runtime
>> will be faster on Linux64, so that's what we recommend.
>>
>> Steve
>>
>
> 

Steve Lass wrote:
> I can give you some general recommendations. For the best place and
> route runtimes, use a 64bit Linux system. If your design is small
> enough to fit into 4G of memory (LX110 or smaller), and you are not
> programming devices (the 32bit cable drivers don't work on a 64bit
> system), you can use the 32bit executables to save memory.
> Otherwise, go ahead and use the 64bit executables. They use more
> memory and the runtime is simular.

Note that it works just fine to install 32-bit ISE on a 64-bit Linux
system, and to install the 64-bit cable drivers.

In my experience, the open source user-space-only cable interface works
far better than the Xilinx-supplied cable drivers anyhow:

    http://www.rmdir.de/~michael/xilinx/

On 2007-08-02, Wei Wang <camwwang@gmail.com> wrote:
> Why only 3GB max of 4GB? thanks, -Wei

The short answer is that the upper 1GB is reserved for the kernel.
If you want a bit more detail you can look at for example the
following article:
http://kerneltrap.org/node/2450

/Andreas

<steve.lass@xilinx.com> wrote in message news:f8tr6p$c9h1@cnn.xilinx.com...
> I can give you some general recommendations. For the best place and route
> runtimes,
> use a 64bit Linux system. If your design is small enough to fit into 4G of
> memory
> (LX110 or smaller), and you are not programming devices (the 32bit cable
> drivers
> don't work on a 64bit system), you can use the 32bit executables to save
> memory.
> Otherwise, go ahead and use the 64bit executables. They use more memory
and
> the runtime is simular.

Is there a 64-bit version of EDK ? If not, can I mix 64 bit ISE with 32 bit
EDK?

Thanks,
/Mikhail

On Aug 3, 1:00 am, <steve.l...@xilinx.com> wrote:
> I can give you some general recommendations. For the best place and route
> runtimes,
> use a 64bit Linux system. If your design is small enough to fit into 4G of
> memory
> (LX110 or smaller), and you are not programming devices (the 32bit cable
> drivers
> don't work on a 64bit system), you can use the 32bit executables to save
> memory.
> Otherwise, go ahead and use the 64bit executables. They use more memory and
> the runtime is simular.
>
> As mentioned earlier, synthesis, map, place and route do not use
> multithreading, so
> you will not get an advantage using multiple processors for a single design.
> However,
> ProjNav is multithreaded so if you are doing different tasks, other
> processors will
> be used. In addition, upcoming software releases will use those processors.
>
> Steve
>
> "MM" <mb...@yahoo.com> wrote in message
>
> news:5hf8n2F3k0uqkU1@mid.individual.net...
>
>
>
> > Hi Steve,
>
> > Could you give us (Xilinx users) some more detailed recommendations on
> > what would be the best platform to run ISE/EDK tools when working on
> > midsize to big designs? Tell us what you are using @ Xilinx? :)
>
> > Thanks,
> > /Mikhail
>
> > <steve.l...@xilinx.com> wrote in message
> >news:f8tksu$caa1@cnn.xilinx.com...
> >> "Wei Wang" <camww...@gmail.com> wrote in message
> >>news:1186091680.680639.251840@z24g2000prh.googlegroups.com...
> >>> Found similar memory recommendations for Xilinx's largest XC5VLX330
> >>> FPGA,
> >>>http://www.xilinx.com/ise/products/memory.htm#v5lx
> >>> only Linux-64 machines are supported, memory recommendation: typical
> >>> 7.2GB and peak 10.6GB.
>
> >> This web page needs to be updated: NT64 is also supported, but runtime
> >> will be faster on Linux64, so that's what we recommend.
>
> >> Steve- Hide quoted text -
>
> - Show quoted text -

What I found was very interesting, it was taking me 12 hours to run
the MAP process before, but yesterday it only took me ~3 hours to run
MAP, and PAR only too took ~40 mins as well.

I was trying to figure out the reasons, then found in *.map *.mrp
files that there was always a map phase which took such a long time as
~10+ hours, and that phrase was always very memory hungry. I was using
Linux64 with 2GB real memory and 4GB swap memory, as I just found that
the real 2GB memory was much smaller than the required peak memory
10.6GB. Yesterday, I was running ISE9.1i for XC5VLX330 on another
Linux64 machine with 11G real memory and 8G swap memory, the there
wasn't any MAP phrase which took a ridiculous ~10+ hours.

Can Xilinx guys shed some more light on the runtime of MAP and PAR,
wrt different memory sizes and CPU cores?

On 2 ao=FBt, 15:15, jjohn...@cs.ucf.edu wrote:

> P.S. Those QX6850's are hard to come by; Dell's overclocked XPS720's
> look sweet, but my company won't spring for overclocked boxes...

Polywell has some desktop computers with QX6850 available. Although
since you're looking at an 8-way workstation (!), QX6850 is probably
not an option. Polywell has AMD or Intel workstations with the CPUs
you're looking at as well.

For one socket, Intel clearly has the edge over AMD I think. For multi-
socket workstations/servers however, I'm not so sure. Benchmarks are
harder to find. I would suspect that the Hypertransport bus would help
AMD close the gap with Intel a little. Their integrated memory
controller probably helps as well in a multi-socket machine.

I searched for benchmarks for the newest 90-nm Opteron but couldn't
find any unfortunately...

Patrick

"Wei Wang" <camwwang@gmail.com> wrote in message 
news:1186135446.310054.313850@g4g2000hsf.googlegroups.com...
>
> What I found was very interesting, it was taking me 12 hours to run
> the MAP process before, but yesterday it only took me ~3 hours to run
> MAP, and PAR only too took ~40 mins as well.
>
> I was trying to figure out the reasons, then found in *.map *.mrp
> files that there was always a map phase which took such a long time as
> ~10+ hours, and that phrase was always very memory hungry. I was using
> Linux64 with 2GB real memory and 4GB swap memory, as I just found that
> the real 2GB memory was much smaller than the required peak memory
> 10.6GB. Yesterday, I was running ISE9.1i for XC5VLX330 on another
> Linux64 machine with 11G real memory and 8G swap memory, the there
> wasn't any MAP phrase which took a ridiculous ~10+ hours.
>
> Can Xilinx guys shed some more light on the runtime of MAP and PAR,
> wrt different memory sizes and CPU cores?
>

Yes, that indeed would be great!

With my current design I found that timing-driven MAP either crashes or 
takes very long time to complete (relative to PAR). Even more interesting is 
that I get much better timing and much faster run times by actually 
disabling timing-driven mapping and use of RLOC constraints in MAP...

/Mikhail

"Wei Wang" <camwwang@gmail.com> wrote in message 
news:1186135446.310054.313850@g4g2000hsf.googlegroups.com...

> Can Xilinx guys shed some more light on the runtime of MAP and PAR,
> wrt different memory sizes and CPU cores?
>
Even though our memory requirement table lists devices, memory is more
dependent on the design and the timing constraints. Since we can't predict
what is in your design, we just give you the typical and max numbers from
our collected test cases.

An example for constraints which will reduce memory is instead of creating
a bunch of individual from to timespecs, you can create timegroups with the
endpoints, then put one timespec on that.

Also, ISE 9.2i is getting an average of 27% improvement in memory
utilization.

I don't have any data regarding runtime of different CPU cores.

Steve