completely open source fpga toolchain

Please bear in mind that this is only an 8-bit ripple-carry adder, and
the tools are still quite crude, but I believe we now have the
first-ever instance of a design being taken through a 100% open-source
flow, all the way from verilog to blinking lights on a programmed device.

Details are here:

  http://research.cs.berkeley.edu/project/slipway/

Again, it's nowhere close to production-ready, but there are already a
lot of doors opening up: programmatic access to the inner PAR loop (ie
incremental runs) plus partial reconfiguration is a very powerful
combination.

More to come.

  - a

-- 
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

Adam Megacz schrieb:
> Please bear in mind that this is only an 8-bit ripple-carry adder, and
> the tools are still quite crude, but I believe we now have the
> first-ever instance of a design being taken through a 100% open-source
> flow, all the way from verilog to blinking lights on a programmed device.
> 
> Details are here:
> 
>   http://research.cs.berkeley.edu/project/slipway/
> 
> Again, it's nowhere close to production-ready, but there are already a
> lot of doors opening up: programmatic access to the inner PAR loop (ie
> incremental runs) plus partial reconfiguration is a very powerful
> combination.

They used Icarus Verilog for synthesis. Synthesis capability has been
removed from icarus Verilog (though the author hopes to reintegrate it
one day) since it was very broken and buggy.

Philipp

On Jul 27, 4:42 am, Philipp Klaus Krause <p...@spth.de> wrote:
> They used Icarus Verilog for synthesis. Synthesis capability has been
> removed from icarus Verilog (though the author hopes to reintegrate it
> one day) since it was very broken and buggy.

That's excessively harsh, and equally said of vendors tools with all
the bugs they have. There have been enough threads go thru here about
those too. So if this is just more open source bashing, please be more
specific, and things will get fixed.

Steve (the author of icarus Verilog) does admit that synthesis in the
current 0.9 development branch is broken right now, due to some major
internal changes in progress, but will be fixed after the 0.9 release
is done. During that transition he expects people can continue to use
0.8 synthesis until it's fixed for 0.9.

I'm sure that if you actually report what you think is "very broken
and buggy" problems, fixes will appear when he (or others) have time.
That that much time between fixes we see for vendors tools which
appear at major release cycles.

Steve reports there are others, besides him, working on synthesis
backends, and when he gets fixes, he generally applies them to the
release tree.

On Jul 29, 9:54 am, fpga_t...@yahoo.com wrote:
> On Jul 27, 4:42 am, Philipp Klaus Krause <p...@spth.de> wrote:
>
> > They used Icarus Verilog for synthesis. Synthesis capability has been
> > removed from icarus Verilog (though the author hopes to reintegrate it
> > one day) since it was very broken and buggy.

> Steve (the author of icarus Verilog) does admit that synthesis in the
> current 0.9 development branch is broken right now, due to some major
> internal changes in progress, but will be fixed after the 0.9 release
> is done. During that transition he expects people can continue to use
> 0.8 synthesis until it's fixed for 0.9.

Oh ... two other notes ... at least in progress development trees are
visible and available with open source projects, and you can certainly
fix problems you find and contribute to the project when you have the
skills and time.

Like vendors tools, when releases show up with major bugs, you do the
same thing ... keep using the previous release until another major
release rolls that you can use (or a patch/update appears).

fpga_toys@yahoo.com schrieb:
> On Jul 27, 4:42 am, Philipp Klaus Krause <p...@spth.de> wrote:
>> They used Icarus Verilog for synthesis. Synthesis capability has been
>> removed from icarus Verilog (though the author hopes to reintegrate it
>> one day) since it was very broken and buggy.
> 
> That's excessively harsh, and equally said of vendors tools with all
> the bugs they have. There have been enough threads go thru here about
> those too. So if this is just more open source bashing, please be more
> specific, and things will get fixed.
> 
> Steve (the author of icarus Verilog) does admit that synthesis in the
> current 0.9 development branch is broken right now, due to some major
> internal changes in progress, but will be fixed after the 0.9 release
> is done. During that transition he expects people can continue to use
> 0.8 synthesis until it's fixed for 0.9.


I remembered 463A2014.7040400@icarus.com, where Steve said:

"CAVEAT: Synthesis in the devel trunk is broken, and has been
temporarily abandoned. There was until very recently precious
little interest in synthesis, so I didn't let it get in the way
of the other tasks I've been working on. Getting synthesis back
on line with the devel branch should be a big job.

Therefore, for now I recommend using the 0.8 branch for synthesis
work, at least for a proof of concept. If there is interest in
putting serious work into it, then getting 0.9 synthesis together
can be worked out later."

> [...]
> Steve reports there are others, besides him, working on synthesis
> backends, and when he gets fixes, he generally applies them to the
> release tree.
>

This is good news, I didn't know that people are working on synthesis
backends. Was there a post on geda-user about it?

Philipp

On 30 Jul., 12:28, Philipp Klaus Krause <p...@spth.de> wrote:
> fpga_t...@yahoo.com schrieb:
>
> > On Jul 27, 4:42 am, Philipp Klaus Krause <p...@spth.de> wrote:
> >> They used Icarus Verilog for synthesis. Synthesis capability has been
> >> removed from icarus Verilog (though the author hopes to reintegrate it
> >> one day) since it was very broken and buggy.
>
> > That's excessively harsh, and equally said of vendors tools with all
> > the bugs they have. There have been enough threads go thru here about
> > those too. So if this is just more open source bashing, please be more
> > specific, and things will get fixed.
>
> > Steve (the author of icarus Verilog) does admit that synthesis in the
> > current 0.9 development branch is broken right now, due to some major
> > internal changes in progress, but will be fixed after the 0.9 release
> > is done. During that transition he expects people can continue to use
> > 0.8 synthesis until it's fixed for 0.9.
>
> I remembered 463A2014.7040...@icarus.com, where Steve said:
>
> "CAVEAT: Synthesis in the devel trunk is broken, and has been
> temporarily abandoned. There was until very recently precious
> little interest in synthesis, so I didn't let it get in the way
> of the other tasks I've been working on. Getting synthesis back
> on line with the devel branch should be a big job.
>
> Therefore, for now I recommend using the 0.8 branch for synthesis
> work, at least for a proof of concept. If there is interest in
> putting serious work into it, then getting 0.9 synthesis together
> can be worked out later."
>
> > [...]
> > Steve reports there are others, besides him, working on synthesis
> > backends, and when he gets fixes, he generally applies them to the
> > release tree.
>
> This is good news, I didn't know that people are working on synthesis
> backends. Was there a post on geda-user about it?
>
> Philipp

there are or have been sure
a while ago I think I got some working AT94K bistream made using the
iverilog front

Antti

Philipp Klaus Krause <pkk@spth.de> writes:
> "CAVEAT: Synthesis in the devel trunk is broken,

Just to clear up any confusion here, I am not using the devel trunk.

  - a

-- 
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

Philipp Klaus Krause <pkk@spth.de> writes:
> "CAVEAT: Synthesis in the devel trunk is broken,

Just to clear up any confusion here, I am not using the devel trunk.

  - a

-- 
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

On Jul 30, 10:36 am, Adam Megacz <meg...@cs.berkeley.edu> wrote:

> Just to clear up any confusion here, I am not using the devel trunk.

I just found out about your work by your post on geda-user and am
interested to
know what the "current projects" are you mentioned in the FCCM paper.
Are there any slipway parts left?  If not I'll be making two, (or
more) for geda-user folk,
done with gEDA tools and put up on one of my sites and/or yours.

WIX looks good too!

John Griessen
Ecosensory

On Jul 30, 4:28 am, Philipp Klaus Krause <p...@spth.de> wrote:
> This is good news, I didn't know that people are working on synthesis
> backends. Was there a post on geda-user about it?

Dunno ... don't watch that email. Just relayed a comment from private
email from Steve.

I responded because of your unkind, broad, unqualified, slamming
assessment of Steve's work:

> On Jul 27, 4:42 am, Philipp Klaus Krause <p...@spth.de> wrote:
>> They used Icarus Verilog for synthesis. Synthesis capability has been
>> removed from icarus Verilog (though the author hopes to reintegrate it
>> one day) since it was very broken and buggy.

Development branches are expected to be sometimes broken and buggy,
but you unjustifiably slammed Steve's work without that qualification.
I, and others, have used Steve's synthesis in past stable releases
without problems .... as well as Steve, for paying work. The issues
I've had with it have all been relatively minor ... and not unlike
similar problems with vendors tool chains.

Not knowing where people are using it and NOT having problems, does
give most open source developers a vacumn for judging both what is
being used, and how much.