dual port ram

I used the verilog language template to create a dual port RAM. The 
initial size that I selected was 64 words x 32 bits. It synthesises OK 
and the synthesis report says that I have 64x32.

I added a reset pin. All synthesises OK.

I thought that I only need 18 to 32 registers. So I changed the address 
size from 6 to 5. I get no change of the dual port ram size.

I changed the data word width from 32 bits to 64 bits. I get no change 
of ram size.

Can I actually create a small dual port ram such as 18 words of 32 bits 
or have I missed some synthesis command. It looks to be more like the 
software is not actually processing the changed source code.

I'm use ISE 9.1. All help gratefully recieved. Andy

"Andy Botterill" <andy@plymouth2.demon.co.uk> wrote in message 
news:46ab58a9$0$642$bed64819@news.gradwell.net...
>I used the verilog language template to create a dual port RAM. The initial 
>size that I selected was 64 words x 32 bits. It synthesises OK and the 
>synthesis report says that I have 64x32.
>
What sort of dual port ram are you trying to infer? Distributed or block?
>
> I added a reset pin. All synthesises OK.
>
What does this reset pin meant to do? Distributed RAM doesn't play with 
reset, the block memory has a reset which only resets the output registers.

Cheers, Syms. 

Symon wrote:
> "Andy Botterill" <andy@plymouth2.demon.co.uk> wrote in message 
> news:46ab58a9$0$642$bed64819@news.gradwell.net...
> 
>>I used the verilog language template to create a dual port RAM. The initial 
>>size that I selected was 64 words x 32 bits. It synthesises OK and the 
>>synthesis report says that I have 64x32.
>>
> 
> What sort of dual port ram are you trying to infer? Distributed or block?

Block ram. I used the 2 clock 2 read/write port template.
> 
>>I added a reset pin. All synthesises OK.
>>
> 
> What does this reset pin meant to do? Distributed RAM doesn't play with 
> reset, the block memory has a reset which only resets the output registers.

Ah. I was intending to use the dual port ram as a register file. The 
register file needs 3 registers (out of 18-20) initialising at reset. Is 
there any way to do this using any of the dual/single port RAM's?

I was tring to compare a register based register file with a dual port 
ram based register file.

Looks like it may not be possible.
> 
> Cheers, Syms. 
> 
> 

On Sat, 28 Jul 2007 18:02:28 +0100, Andy Botterill
<andy@plymouth2.demon.co.uk> wrote:

>Ah. I was intending to use the dual port ram as a register file. The 
>register file needs 3 registers (out of 18-20) initialising at reset. Is 
>there any way to do this using any of the dual/single port RAM's?

See below - in FPGAs, yes.  In other technologies, no.  
For this problem on this scale, the technique I usually
use is to build the DPRAM in the ordinary way, and then to build a 
regular collection of flip-flops with one FF per RAM location.
These FFs are reset to 0 at power-up, and are changed to 1 
whenever the corresponding RAM location is written - an easy
thing to arrange.  The trick, of course, is that when you READ
one of the RAM locations you first check the "have I been 
written" register - and, if it's zero, then you substitute
the desired power-up reset value in place of the RAM contents.

HOWEVER, you *can* initialise the contents of any Xilinx
RAM at configuration (I think - betcha there are some 
exceptions I don't know about).  Trawl the docs for "memory
initialization file" or somesuch.  Plenty of people here will
have that information at their fingertips; I don't.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley wrote:
> On Sat, 28 Jul 2007 18:02:28 +0100, Andy Botterill
> <andy@plymouth2.demon.co.uk> wrote:
> 
> 
>>Ah. I was intending to use the dual port ram as a register file. The 
>>register file needs 3 registers (out of 18-20) initialising at reset. Is 
>>there any way to do this using any of the dual/single port RAM's?
> 
> 
> See below - in FPGAs, yes.  In other technologies, no.  
> For this problem on this scale, the technique I usually
> use is to build the DPRAM in the ordinary way, and then to build a 
> regular collection of flip-flops with one FF per RAM location.
> These FFs are reset to 0 at power-up, and are changed to 1 
> whenever the corresponding RAM location is written - an easy
> thing to arrange.  The trick, of course, is that when you READ
> one of the RAM locations you first check the "have I been 
> written" register - and, if it's zero, then you substitute
> the desired power-up reset value in place of the RAM contents.

Only three registers need a reset change of state. That will simplify 
the code. I'll give it a try and get back to you.
> 
> HOWEVER, you *can* initialise the contents of any Xilinx
> RAM at configuration (I think - betcha there are some 
> exceptions I don't know about).  Trawl the docs for "memory
> initialization file" or somesuch.  Plenty of people here will
> have that information at their fingertips; I don't.

Hopefully I won't have to use this method.

Thanks for everyones help.

Andy,

If you like to use the BRAM, it may be loaded with whatever you please 
by using a software tool to take a hex file, and place it into the 
bitstream (effectively makes the RAM a ROM).

Since the BRAM is loaded from the bitstream, the default, or initial 
condition is all zeroes.

This is also true of LUTRAM (it is all 0's to start with, because that 
is what is in the bitstream).

There is a way to specify LUT contents for the bitstream, but I don't 
have that handy (net connection at home is slow to download 6 Mb user 
guides!).

Austin

On 2007-07-28, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:
> HOWEVER, you *can* initialise the contents of any Xilinx
> RAM at configuration

But then you can't just 'reset' your design.  You have to reconfigure
from the bitstream to truly reset.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

RAMs do not have a parallel reset for a very simple reason: It would
be very expensive, adding a gate to each cell, plus routing the reset
input all over the RAM area.
Over the past 50 or more years, designers have learned to live with
the fact that you cannot just instantly reset the whole RAM. And life
goes on...
Peter Alfke
=========================
On Jul 28, 5:06 pm, Ben Jackson <b...@ben.com> wrote:
> On 2007-07-28, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:
>
> > HOWEVER, you *can* initialise the contents of any Xilinx
> > RAM at configuration
>
> But then you can't just 'reset' your design.  You have to reconfigure
> from the bitstream to truly reset.
>
> --
> Ben Jackson AD7GD
> <b...@ben.com>http://www.ben.com/

Peter Alfke wrote:
> RAMs do not have a parallel reset for a very simple reason: It would
> be very expensive, adding a gate to each cell, plus routing the reset
> input all over the RAM area.
> Over the past 50 or more years, designers have learned to live with
> the fact that you cannot just instantly reset the whole RAM. And life
> goes on...

I agree with you.

I am trying to design a register file as an exercise in design. I have 3 
different concepts. Two of the concepts are using traditional registers 
and the third is using a dual port ram.

They all have to work as register files and have a reset operation which 
is consistent with each other and the original design. If I cannot reset 
the register file when using a dual port ram then I've done the wrong thing.

Andy

> Peter Alfke
> =========================
> On Jul 28, 5:06 pm, Ben Jackson <b...@ben.com> wrote:
> 
>>On 2007-07-28, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:
>>
>>
>>>HOWEVER, you *can* initialise the contents of any Xilinx
>>>RAM at configuration
>>
>>But then you can't just 'reset' your design.  You have to reconfigure
>>from the bitstream to truly reset.
>>
>>--
>>Ben Jackson AD7GD
>><b...@ben.com>http://www.ben.com/
> 
> 
> 

On Sat, 28 Jul 2007 19:06:06 -0500, Ben Jackson <ben@ben.com> wrote:

>On 2007-07-28, Jonathan Bromley wrote:
>> HOWEVER, you *can* initialise the contents of any Xilinx
>> RAM at configuration
>
> But then you can't just 'reset' your design.  You have to
> reconfigure from the bitstream to truly reset.

Yes.  But the solution I offered - one "I have been written"
register bit per RAM location - doesn't scale well; it's fine
for up to a few dozen locations, no more.

If you can arrange that the RAM locations whose initial value
matters to you are all in a small piece of address space, you
can easily modify the "I have been written" trick so that
it applies only to the small part of the memory that has the
initialisation requirement.

More generally, it is not unreasonable to consider modifying
your system's control state machine so that its first action
after reset is to scribble the initialisation values into RAM,
maybe by block-copy out of another memory configured as ROM
with the reset values in it.

As Peter said, it's not practical to reset a big memory,
and people have lived with this for ever.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.