DDR Simulation Model

During my work with the XUP development board another problem occured
when I tried to use the on-board DDR-SDRAM. A data stream is written
into the RAM using the PLB bus and burst mode (16 x 64 bit). When I
read the data from the RAM using the Power PC after some time an error
occurs. It looks like one 64 bit word has not been written into the
RAM (or it has been overwritten - I am not sure about this).
When I use the Block RAM of the Virtex-II Pro instead everything is
fine. I do not change anything but the address. Same protocol is used
for both RAMs.

My problem is that I do not have a simulation model for the DDR RAM.
It is a Kingston KVR266X64C25/256. All I can do during simulation is
to look what the PLB DDR controller is writing to the output pins. And
the simulation does not show any wrong behavior at this point. I can
not perform any read accesses since there is no RAM model atttached.
So currently for tests the only way is to use the real board but here
I can not see, what is happening.
Does anybody know, where I can get a simulation model for this RAM? I
have searched the Kingston page. I have sent them an E-Mail (still
waiting for response). I have tried Google but I could not find
anything. Same here.
Thanks in advance

Sebastian Goller

On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote:

> During my work with the XUP development board another problem occured
> when I tried to use the on-board DDR-SDRAM. A data stream is written
> into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read
> the data from the RAM using the Power PC after some time an error
> occurs. It looks like one 64 bit word has not been written into the RAM
> (or it has been overwritten - I am not sure about this). When I use the
> Block RAM of the Virtex-II Pro instead everything is fine. I do not
> change anything but the address. Same protocol is used for both RAMs.
> 
> My problem is that I do not have a simulation model for the DDR RAM. It
> is a Kingston KVR266X64C25/256. All I can do during simulation is to
> look what the PLB DDR controller is writing to the output pins. And the
> simulation does not show any wrong behavior at this point. I can not
> perform any read accesses since there is no RAM model atttached. So
> currently for tests the only way is to use the real board but here I can
> not see, what is happening.
> Does anybody know, where I can get a simulation model for this RAM? I
> have searched the Kingston page. I have sent them an E-Mail (still
> waiting for response). I have tried Google but I could not find
> anything. Same here.
> Thanks in advance
> 
> Sebastian Goller

Kingston makes DIMMs not RAMs. You can find RAM models on Micron's 
website.

On Jul 31, 6:34 am, s...@hrz.tu-chemnitz.de wrote:
> During my work with the XUP development board another problem occured
> when I tried to use the on-board DDR-SDRAM. A data stream is written
> into the RAM using the PLB bus and burst mode (16 x 64 bit). When I
> read the data from the RAM using the Power PC after some time an error
> occurs. It looks like one 64 bit word has not been written into the
> RAM (or it has been overwritten - I am not sure about this).
> When I use the Block RAM of the Virtex-II Pro instead everything is
> fine. I do not change anything but the address. Same protocol is used
> for both RAMs.
>
> My problem is that I do not have a simulation model for the DDR RAM.
> It is a Kingston KVR266X64C25/256. All I can do during simulation is
> to look what the PLB DDR controller is writing to the output pins. And
> the simulation does not show any wrong behavior at this point. I can
> not perform any read accesses since there is no RAM model atttached.
> So currently for tests the only way is to use the real board but here
> I can not see, what is happening.
> Does anybody know, where I can get a simulation model for this RAM? I
> have searched the Kingston page. I have sent them an E-Mail (still
> waiting for response). I have tried Google but I could not find
> anything. Same here.
> Thanks in advance
>
> Sebastian Goller

Hi S,
When you write data into Block RAM of Xilinx FPGA, you provide address
and data in the same clock. When reading, first clock is to provide
address, then reading its data from data bus on second clock due to
one clock delay of Block RAM.

DDR RAM is totally different from Block RAM of Xilinx. It has some
defined bus activities to get data written or read. You cannot
directly read or write by PowerPC. There must be some logic between
them to access approprite data.

You must read its manual carefully and understand its read and write
rules that is at least 20 full pages long.

Weng

On Jul 31, 4:54 pm, "B. Joshua Rosen"
<bjro...@polybusPleaseDontSpamMe.com> wrote:
> On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote:
> > During my work with the XUP development board another problem occured
> > when I tried to use the on-board DDR-SDRAM. A data stream is written
> > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read
> > the data from the RAM using the Power PC after some time an error
> > occurs. It looks like one 64 bit word has not been written into the RAM
> > (or it has been overwritten - I am not sure about this). When I use the
> > Block RAM of the Virtex-II Pro instead everything is fine. I do not
> > change anything but the address. Same protocol is used for both RAMs.
>
> > My problem is that I do not have a simulation model for the DDR RAM. It
> > is a Kingston KVR266X64C25/256. All I can do during simulation is to
> > look what the PLB DDR controller is writing to the output pins. And the
> > simulation does not show any wrong behavior at this point. I can not
> > perform any read accesses since there is no RAM model atttached. So
> > currently for tests the only way is to use the real board but here I can
> > not see, what is happening.
> > Does anybody know, where I can get a simulation model for this RAM? I
> > have searched the Kingston page. I have sent them an E-Mail (still
> > waiting for response). I have tried Google but I could not find
> > anything. Same here.
> > Thanks in advance
>
> > Sebastian Goller
>
> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's
> website.

Thanks for your answer. I have taken a look at http://www.micron.com
(Design Support etc.) The problem is that I can not find a module that
has the specifications of the RAM I use in my design.
The KVR2666X64C25//256 has the following specs (according to the data
sheet):

- 256MB 32M x 64-Bit
- DDR266
- CL2.5
- 184-Pin DIMM

There is no module on Micron's site that has these specs. Every DDR266-
Module has a CL2.0. I can only choose between pin count 66 and 66-
ball. A depth of 256 MB is not available for DDR266.
I have looked at my design. There are 106 pins used for the interface
between the PLB DDR controller and the RAM module. So a pin count of
66 does not seem useful to me.
I am sorry if ask very stupid questions, but it is the first time I
use DDR SDRAM.

On Jul 31, 8:30 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Jul 31, 6:34 am, s...@hrz.tu-chemnitz.de wrote:
>
>
>
> > During my work with the XUP development board another problem occured
> > when I tried to use the on-board DDR-SDRAM. A data stream is written
> > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I
> > read the data from the RAM using the Power PC after some time an error
> > occurs. It looks like one 64 bit word has not been written into the
> > RAM (or it has been overwritten - I am not sure about this).
> > When I use the Block RAM of the Virtex-II Pro instead everything is
> > fine. I do not change anything but the address. Same protocol is used
> > for both RAMs.
>
> > My problem is that I do not have a simulation model for the DDR RAM.
> > It is a Kingston KVR266X64C25/256. All I can do during simulation is
> > to look what the PLB DDR controller is writing to the output pins. And
> > the simulation does not show any wrong behavior at this point. I can
> > not perform any read accesses since there is no RAM model atttached.
> > So currently for tests the only way is to use the real board but here
> > I can not see, what is happening.
> > Does anybody know, where I can get a simulation model for this RAM? I
> > have searched the Kingston page. I have sent them an E-Mail (still
> > waiting for response). I have tried Google but I could not find
> > anything. Same here.
> > Thanks in advance
>
> > Sebastian Goller
>
> Hi S,
> When you write data into Block RAM of Xilinx FPGA, you provide address
> and data in the same clock. When reading, first clock is to provide
> address, then reading its data from data bus on second clock due to
> one clock delay of Block RAM.
>
> DDR RAM is totally different from Block RAM of Xilinx. It has some
> defined bus activities to get data written or read. You cannot
> directly read or write by PowerPC. There must be some logic between
> them to access approprite data.
>
> You must read its manual carefully and understand its read and write
> rules that is at least 20 full pages long.
>
> Weng

Hi Tianxiang,

thanks for your answer. There is a DDR controller in my design. All
components are connected via PLB bus. So everything I have to do is to
use the PLB protocol. The controller will handle the rest.
What I do not understand is that some data is written and read
correctly. There is only one 64 bit word which is missing. The PowerPC
starts reading at the base address of the DDR RAM (0x00000000). I use
a simple pointer PMEM and assign the value in PMEM to another
variable. After the data has been read from the RAM PMEM is increased
by 4 (32 bit data width). This works until PMEM is 1152. Then the
error occurs. After this error everthing looks fine again.

On Jul 31, 4:54 pm, "B. Joshua Rosen"
<bjro...@polybusPleaseDontSpamMe.com> wrote:
> On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote:
> > During my work with the XUP development board another problem occured
> > when I tried to use the on-board DDR-SDRAM. A data stream is written
> > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read
> > the data from the RAM using the Power PC after some time an error
> > occurs. It looks like one 64 bit word has not been written into the RAM
> > (or it has been overwritten - I am not sure about this). When I use the
> > Block RAM of the Virtex-II Pro instead everything is fine. I do not
> > change anything but the address. Same protocol is used for both RAMs.
>
> > My problem is that I do not have a simulation model for the DDR RAM. It
> > is a Kingston KVR266X64C25/256. All I can do during simulation is to
> > look what the PLB DDR controller is writing to the output pins. And the
> > simulation does not show any wrong behavior at this point. I can not
> > perform any read accesses since there is no RAM model atttached. So
> > currently for tests the only way is to use the real board but here I can
> > not see, what is happening.
> > Does anybody know, where I can get a simulation model for this RAM? I
> > have searched the Kingston page. I have sent them an E-Mail (still
> > waiting for response). I have tried Google but I could not find
> > anything. Same here.
> > Thanks in advance
>
> > Sebastian Goller
>
> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's
> website.

I have taken a look at the RAM Module. There is some more information
on the RAM chips:

0516      1-1
MT         46V32M8
TG         -5B G

What does this mean and how can I use it to find the correct
simulation model?

> Thanks for your answer. I have taken a look at http://www.micron.com
> (Design Support etc.) The problem is that I can not find a module that
> has the specifications of the RAM I use in my design.
> The KVR2666X64C25//256 has the following specs (according to the data
> sheet):
>
> - 256MB 32M x 64-Bit
> - DDR266
> - CL2.5
> - 184-Pin DIMM

	Well :

	TYpe KVR266X64C25 in Google
	Get the spec sheet (first link)
	Count chips on module (result : 16 chips)
	So, it has 16x 32Mx4-bit chips making 32Mx64 bits

	Then, either get a module and look at what chips it actually uses, or :
	Go to Micron's site and search 32Mx4-bit, CL2.5 modules

	MT46V32M4P-75
	MT46V32M4TG-75

	Hint : those are DDR266B, not DDR266

> There is no module on Micron's site that has these specs. Every DDR266-

	That's because you got a Kingston module ;) not Micron

> Module has a CL2.0. I can only choose between pin count 66 and 66-
> ball. A depth of 256 MB is not available for DDR266.
> I have looked at my design. There are 106 pins used for the interface
> between the PLB DDR controller and the RAM module. So a pin count of
> 66 does not seem useful to me.

	That's because there are 16 chips on your Kingston, not 1.
	If you check the pinout of the 184-pin DDR module you'll notice that  
there are something like 106 useful pins, the rest is power supply and  
ground...

> I am sorry if ask very stupid questions, but it is the first time I
> use DDR SDRAM.

	Are you routing the PCB ?

> I have taken a look at the RAM Module. There is some more information
> on the RAM chips:
>
> 0516      1-1
> MT         46V32M8
> TG         -5B G
>
> What does this mean and how can I use it to find the correct
> simulation model?

	Sorry, did not read this before writing the previous email ;)

	Look for a model of a Micron chip like :

	MT46V32M8-5BG

	or something. Note you'll have to instantiate the model 16 times (since  
you got 16 chips on your RAM stick) and connect the nets accordingly.

On Wed, 01 Aug 2007 02:35:12 -0700, Sebastian Goller
<sego@hrz.tu-chemnitz.de> wrote:

>>
>> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's
>> website.
>
>I have taken a look at the RAM Module. There is some more information
>on the RAM chips:
>
>0516      1-1
>MT         46V32M8
>TG         -5B G
>
>What does this mean and how can I use it to find the correct
>simulation model?

This is a Micron Technology RAM; look for a Micron model which matches
46V32M8 - or find how Micron translate device markings to part numbers.

In the event you need a VHDL model, Micron may not offer VHDL models for
newer devices for some reason, you may need a model from the Hynix
equivalent part.

Re: the error at pointer = 1152 - this is an odd number. Does this error
coincide with a refresh cycle?

- Brian

> Re: the error at pointer = 1152 - this is an odd number. Does this error
> coincide with a refresh cycle?
>
> - Brian

Hi Brian,

I have no idea since I am currently testing the design on the board.
After I have a simulation model for the DDR RAM I can check this in
the simulation.