DDR Simulation Model

Hi PFC and Brian,

thanks alot for your answers. I am now about to find out, which RAM
model I can use and ... believe it or not - I have some trouble. ;-)

The datasheet of the Kingston DIMM says that this is DDR266 with a
clock cycle time of 7.5 ns. CL = 2.5

Like Brian already said the RAM modules are Micron products. According
to the Micron datasheets TG -5B G means that this is a RAM module with
a clock cycle time of 5.0 ns. CL = 3.0. The Appendix G means Revision
x4, x8. I have no idea what this means. It does not seem to be very
important.
The problem is that TG -5B is only available for DDR400B on the Micron
page. There are two models available:

MT46V32M8P-5B
MT46V32M8TG-5B

The only difference is the package which should not be important for
the simulation. So the question is: Can I use this model? I am asking
this question before I give it a try, because I know it will be a lot
of fun to implement this model in my Xilinx EDK design.

Sebastian Goller wrote:
> On Jul 31, 4:54 pm, "B. Joshua Rosen"
> <bjro...@polybusPleaseDontSpamMe.com> wrote:
>> On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote:
>>> During my work with the XUP development board another problem occured
>>> when I tried to use the on-board DDR-SDRAM. A data stream is written
>>> into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read
>>> the data from the RAM using the Power PC after some time an error
>>> occurs. It looks like one 64 bit word has not been written into the RAM
>>> (or it has been overwritten - I am not sure about this). When I use the
>>> Block RAM of the Virtex-II Pro instead everything is fine. I do not
>>> change anything but the address. Same protocol is used for both RAMs.
>>> My problem is that I do not have a simulation model for the DDR RAM. It
>>> is a Kingston KVR266X64C25/256. All I can do during simulation is to
>>> look what the PLB DDR controller is writing to the output pins. And the
>>> simulation does not show any wrong behavior at this point. I can not
>>> perform any read accesses since there is no RAM model atttached. So
>>> currently for tests the only way is to use the real board but here I can
>>> not see, what is happening.
>>> Does anybody know, where I can get a simulation model for this RAM? I
>>> have searched the Kingston page. I have sent them an E-Mail (still
>>> waiting for response). I have tried Google but I could not find
>>> anything. Same here.
>>> Thanks in advance
>>> Sebastian Goller
>> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's
>> website.
> 
> Thanks for your answer. I have taken a look at http://www.micron.com
> (Design Support etc.) The problem is that I can not find a module that
> has the specifications of the RAM I use in my design.
> The KVR2666X64C25//256 has the following specs (according to the data
> sheet):
> 
> - 256MB 32M x 64-Bit
> - DDR266
> - CL2.5
> - 184-Pin DIMM
> 
> There is no module on Micron's site that has these specs. Every DDR266-
> Module has a CL2.0. I can only choose between pin count 66 and 66-
> ball. A depth of 256 MB is not available for DDR266.
> I have looked at my design. There are 106 pins used for the interface
> between the PLB DDR controller and the RAM module. So a pin count of
> 66 does not seem useful to me.
> I am sorry if ask very stupid questions, but it is the first time I
> use DDR SDRAM.
> 
You'll have to use a 'generate' statement to set up an array of Micron 
DRAM models so that it matches the configuration of the Kingston DIMM. 
There are some `defines (in the Verilog version) that allow you to 
configure the particular flavor of DRAM.

If you are doing an RTL simulation (i.e., no IDELAY UNISIMs) you will be 
assuming that your timing is correct.  To get a more accurate model, you 
need to use wires with bidirectional delays to model the PCB and IOB 
delay.  One of the biggest problems with making your own DRAM interface 
is getting the return data to line up with your local clock.  -Kevin

On Wed, 01 Aug 2007 06:36:14 -0700, Sebastian Goller
<sego@hrz.tu-chemnitz.de> wrote:

>Hi PFC and Brian,
>
>thanks alot for your answers. I am now about to find out, which RAM
>model I can use and ... believe it or not - I have some trouble. ;-)
>
>The datasheet of the Kingston DIMM says that this is DDR266 with a
>clock cycle time of 7.5 ns. CL = 2.5
>
>Like Brian already said the RAM modules are Micron products. According
>to the Micron datasheets TG -5B G means that this is a RAM module with
>a clock cycle time of 5.0 ns. CL = 3.0. 

Clocking it at 5ns, it would need CL=3.0. I believe this means at 7.5ns
it should support CL=2.5 comfortably; check the datasheet to confirm
that you can set the Mode Register correctly for the CL value you want.

>The only difference is the package which should not be important for
>the simulation. So the question is: Can I use this model? I am asking
>this question before I give it a try, because I know it will be a lot
>of fun to implement this model in my Xilinx EDK design.

Is it available in the language you are using?  If it's only available
in Verilog and EDK is still only VHDL, your simulator needs to support
both languages. I don't know why Micron omit some models in VHDL.

Otherwise you can still simulate without it, to check for collisions
between refresh and access.

- Brian

Okay, meanwhile I got the DDR model implemented in my design. The
testbench compiles without errors and warnings and...the DDR model
does not work. In fact every write access is accepted. But when it
comes to read accesses an error occurs. I can see in the waveform that
the requested data appears on the DDR_DQ bus and is transmitted to the
DDR controller. But it never appears on the PLB bus.

The following message is written in the transcript:

 ** Warning: PLB IPIF data phase timeout assertion....  Addressed
Target did not respond!
#    Time: 515160 ns  Iteration: 4  Instance: /xup_morpheus7_wrapper/
xup_morpheus7_1/ddr_256mb_32mx64_rank1_row13_col10_cl2_5/
ddr_256mb_32mx64_rank1_row13_col10_cl2_5/wo_ecc/plb_ipif_i/
i_slave_attachment

But when I take a look at the waveform the signals of the master/slave-
protocol look fine to me. The DDR controller accepts the read request
from my design. And after some time the the acknowledge signal is
assigned (bus2ip_mstrdack = '1' and bus2ip_mstlastack = '1'). So even
the time limit which causes the message is exceeded the DDR controller
handles the read request. But the transmitted data is always
0x00000000.

Does anybody know, how to solve this problem? Is it a timing issue? I
use the SG75 configuration for my model. The parameters are below or
equal to the parameters of the Kingston module. I think this should
work, shouldn't it? I also created the RAM module by myself. So I did
not use the DIMM file parameters. I will try to compile a complete
DIMM instead of 8 single RAM modules. But I don't think that this will
change a lot since I copied the signals assignments from the DIMM file.