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Altera Cyclone II and Cyclone III "distributed" RAM?

Started by Ioiod August 1, 2007
I looked on Altera's website, but I could not find any description on how
distributed (LUT-based) RAM works on the CYclone II/III family.

FOr the Stratix III, I see Altera called this feature "M-LAB."  Am I
missing something obvious?  Or do the Cyclone family simply not
supported distributed RAM? 


Ioiod wrote:

> I looked on Altera's website, but I could not find any description on how > distributed (LUT-based) RAM works on the CYclone II/III family. > > FOr the Stratix III, I see Altera called this feature "M-LAB." Am I > missing something obvious? Or do the Cyclone family simply not > supported distributed RAM?
Nope, Altera doesn't support distributed RAM in the Cyclone series. Then again, the Cyclone III has a _lot_ of block RAM. Best regards, Ben
On Jul 31, 9:37 pm, "Ioiod" <a...@tht.com> wrote:
> I looked on Altera's website, but I could not find any description on how > distributed (LUT-based) RAM works on the CYclone II/III family.
LUT-based RAM is a Xilinx specific thing that I'm sure is heavily protected. Cyclone I and II only have M4K as hard blocks, though you can use it as two one-port memories. For tiny RAMs making them out of LEs. Cyclone III is the same except the blocks are twice as big (M9K).
> FOr the Stratix III, I see Altera called this feature "M-LAB."
MLAB are one of three different kinds of hard memory blocks. They are not LUT RAM.
> Am I > missing something obvious? Or do the Cyclone family simply not > supported distributed RAM?
They do not support Xilinx style LUT RAM, no. I'm not saying that LUT RAM aren't useful, but they do not come for free and it's all about the tradeoffs. Not speaking for or associated with Altera. Tommy
Hi Tommy,

> > For the Stratix III, I see Altera called this feature "M-LAB." > MLAB are one of three different kinds of hard memory blocks. They are > not LUT RAM.
The MLAB is a block that can function either as a normal LAB or as a 640-bit (32x20 or 64x10) memory; half of the logic blocks in Stratix III are MLABs, and half are logic-only LABs. You are right that there is a trade-off providing hybrid logic/memory capabilities in a device. There is additional circuitry that costs silicon area -- is that area better spent on conversion capability or should it just be spent directly on more area efficient but dedicated RAMs? In Stratix III, the circuitry necessary for RAM mode in MLAB is shared amoung all the ALMs in the MLAB, reducing the silicon area penalty associated with other techniques for combining logic and memory functionality. Readers are correct that Cyclone III does not support any form of hybrid logic/memory block, but the architecture is quite RAM rich as it stands. Regards, Paul Leventis Altera Corp.