Specifying LVDS I/O's in Xilinx FPGA's

Hi,

Can someone please point me in the right direction.

I attempted to define my LVDS inputs via the UCF file for my Xilinx
spartan xc3s1500.

NET data_in                LOC = F19   | IOSTANDARD = LVDS_25   ;

the Xilinx answer record impies that this will work OK.

http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187

Unfortunately I get the following warning, and the input is set to a
standard LVCMOS25.

WARNING:Pack:946 - The I/O component data_in has an illegal I/O
   standard value.  Components of type IOB do not support I/O standard
LVDS_25.
   Please correct the IOSTANDARD property value.

I am using ISE 8.2 (Release 8.2.03i Map I.34)

Any ideas what I am doing wrong? Do I need to istantiate the I/O
buffers?

Thanks for any input,

Steven

<moogyd@yahoo.co.uk> wrote in message 
news:1186593169.119748.316150@q75g2000hsh.googlegroups.com...
> Hi,

> I attempted to define my LVDS inputs via the UCF file for my Xilinx
> spartan xc3s1500.
>
> NET data_in                LOC = F19   | IOSTANDARD = LVDS_25   ;
>
>
> WARNING:Pack:946 - The I/O component data_in has an illegal I/O
>   standard value.  Components of type IOB do not support I/O standard
> LVDS_25.
>   Please correct the IOSTANDARD property value.
>
Hi Steven,
I usually instantiate the IBUFDS (see libraries guide) in my HDL and go from 
there. Don't forget your terminations...

INST "LVDS_P"           DIFF_TERM = TRUE;
INST "LVDS_N"           DIFF_TERM = TRUE;

Also, the tools sometimes get their knickers in a twist about 3.3V and 2.5V 
banks. Googling should solve that for you.

HTH., Syms.

Do you realize that the LVDS *is* a differential signals and requires two 
pins to be defined in the design file?


<moogyd@yahoo.co.uk> wrote in message 
news:1186593169.119748.316150@q75g2000hsh.googlegroups.com...
> Hi,
>
> Can someone please point me in the right direction.
>
> I attempted to define my LVDS inputs via the UCF file for my Xilinx
> spartan xc3s1500.
>
> NET data_in                LOC = F19   | IOSTANDARD = LVDS_25   ;
>
> the Xilinx answer record impies that this will work OK.
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187
>
> Unfortunately I get the following warning, and the input is set to a
> standard LVCMOS25.
>
> WARNING:Pack:946 - The I/O component data_in has an illegal I/O
>   standard value.  Components of type IOB do not support I/O standard
> LVDS_25.
>   Please correct the IOSTANDARD property value.
>
> I am using ISE 8.2 (Release 8.2.03i Map I.34)
>
> Any ideas what I am doing wrong? Do I need to istantiate the I/O
> buffers?
>
> Thanks for any input,
>
> Steven 

defparam buf_100.IOSTANDARD = "LVPECL_25";
defparam buf_103.IOSTANDARD = "LVPECL_25";

IBUFDS        buf_100    (.I(pad_dsp_adc_fsync_cmd_p), .IB 
(pad_dsp_adc_fsync_cmd_n), .O(dsp_adc_fsync_cmd) );
OBUFDS      buf_103   (.I(adc_dsp_sdo_q_p),       .O(pad_adc_dsp_sdo_p), 
.OB(pad_adc_dsp_sdo_n) );

Always check the following doc file for good reference to primitives :
/Xilinx/doc/useglish/books/lib/lib.pdf

-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.
Colorado Based Xilinx Consultant

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


<moogyd@yahoo.co.uk> wrote in message 
news:1186593169.119748.316150@q75g2000hsh.googlegroups.com...
> Hi,
>
> Can someone please point me in the right direction.
>
> I attempted to define my LVDS inputs via the UCF file for my Xilinx
> spartan xc3s1500.
>
> NET data_in                LOC = F19   | IOSTANDARD = LVDS_25   ;
>
> the Xilinx answer record impies that this will work OK.
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187
>
> Unfortunately I get the following warning, and the input is set to a
> standard LVCMOS25.
>
> WARNING:Pack:946 - The I/O component data_in has an illegal I/O
>   standard value.  Components of type IOB do not support I/O standard
> LVDS_25.
>   Please correct the IOSTANDARD property value.
>
> I am using ISE 8.2 (Release 8.2.03i Map I.34)
>
> Any ideas what I am doing wrong? Do I need to istantiate the I/O
> buffers?
>
> Thanks for any input,
>
> Steven
> 

On 8 Aug, 19:12, moo...@yahoo.co.uk wrote:
> Hi,
>
> Can someone please point me in the right direction.
>
> I attempted to define my LVDS inputs via the UCF file for my Xilinx
> spartan xc3s1500.
>
> NET data_in                LOC = F19   | IOSTANDARD = LVDS_25   ;
>
> the Xilinx answer record impies that this will work OK.
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187
>
> Unfortunately I get the following warning, and the input is set to a
> standard LVCMOS25.
>
> WARNING:Pack:946 - The I/O component data_in has an illegal I/O
>    standard value.  Components of type IOB do not support I/O standard
> LVDS_25.
>    Please correct the IOSTANDARD property value.
>
> I am using ISE 8.2 (Release 8.2.03i Map I.34)
>
> Any ideas what I am doing wrong? Do I need to istantiate the I/O
> buffers?
>
> Thanks for any input,
>
> Steven

Thanks for all the responses.

I instantiated the buffers directly in the HDL with no problems.

I know that the S/W is "free", but I don't know why the documentation
implies that you can just specify the buffers in the UCF (I had the
same issue with BUFG's).

Anyway, thanks again,

Steven