Synthesizing fixed_pkg in ISE 9.2

Hi,

I'm trying to synthesize a design with the fixed_pkg package in Xilinx
ISE 9.2. I'm using the version adapted for Xilinx from
http://www.eda-stds.org/fphdl/vhdl.html. Compilation works fine, but
after that I get the following, not exactly helpful error message:

=========================================================================
*                     Design Hierarchy Analysis
*
=========================================================================
ERROR:Xst:2683 - Unexpected error found while building hierarchy.
-->

This happens both with the synthesis test from the website above and
with my own trivial example (attached at the end of the post). You can
get the complete test project from http://www.mikrocontroller.net/attachment/25445/fixpt-test.zip.

Has anyone found a workaround to use fixed_pkg with ISE?

Thanks,
Andreas



Attachment:
architecture rtl of top is
  signal x, y : sfixed (3 downto -3);
begin
  x <= to_sfixed(in1, 3, -3);
  y <= x * 2;
  out1 <= to_slv(y);
end rtl;

Andreas Schwarz wrote:

> Has anyone found a workaround to use fixed_pkg with ISE?

I haven't even tried since the
author of the package reported:

"After fixing everything, it gave me the error:

INTERNAL_ERROR:Xst:cmain.c:3111:1.8.6.1 -  To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com

This is a "use at your own risk" one I guess.  I would
recommend Synplicity, which seems to work much better."

Mike Treseler wrote:
> Andreas Schwarz wrote:
> 
>> Has anyone found a workaround to use fixed_pkg with ISE?
> 
> I haven't even tried since the
> author of the package reported:
> 
> "After fixing everything, it gave me the error:
> 
> INTERNAL_ERROR:Xst:cmain.c:3111:1.8.6.1 -  To resolve this error, please
> consult the Answers Database and other online resources at
> http://support.xilinx.com
> 
> This is a "use at your own risk" one I guess.  I would
> recommend Synplicity, which seems to work much better."

I am the author.

Xilinx said that they were going to fix this in 9.3.  I have not had a 
chance to check it out yet, but I would try that first.

On 14 Aug., 03:52, David Bishop <dbis...@vhdl.org> wrote:
> Xilinx said that they were going to fix this in 9.3.  I have not had a
> chance to check it out yet, but I would try that first.

Thanks for the info. 9.3 isn't released yet, do you have any idea when
it will be?

Andreas

Andreas Schwarz wrote:
> On 14 Aug., 03:52, David Bishop <dbis...@vhdl.org> wrote:
>> Xilinx said that they were going to fix this in 9.3.  I have not had a
>> chance to check it out yet, but I would try that first.
> 
> Thanks for the info. 9.3 isn't released yet, do you have any idea when
> it will be?

I'd use Synplicity.  I've been using 8.803 with these packages.

There is no ISE 9.3. Maybe they meant ISE 9.2.03i  (service pack 3)
which is scheduled to release September 14.

Steve

"Andreas Schwarz" <usenet@andreas-s.net> wrote in message 
news:1187203614.592844.20690@d55g2000hsg.googlegroups.com...
> On 14 Aug., 03:52, David Bishop <dbis...@vhdl.org> wrote:
>> Xilinx said that they were going to fix this in 9.3.  I have not had a
>> chance to check it out yet, but I would try that first.
>
> Thanks for the info. 9.3 isn't released yet, do you have any idea when
> it will be?
>
> Andreas
> 

There is a nice fixed-point package from Doulos which I successfully
used in the past. Look it up on their website.

On Tue, 21 Aug 2007 03:25:47 -0700, Manny <mloulah@hotmail.com> wrote:

>There is a nice fixed-point package from Doulos which I successfully
>used in the past. Look it up on their website.

Manny, 

thanks for the free publicity, but please DON'T use it...
there are a few rather significant bugs with signed 
arithmetic, and it's not as complete as the IEEE packages.

I wish I had worked more closely with David Bishop on this,
because I believe my (Doulos) package has a few features that
are worth having; but it's far too late now, the IEEE package
is far better developed, and it has a test suite - something
I should have done in the first place, but never had time to do.

I PROMISE to take the packages down from our website before the
end of the week, and instead leave a pointer to the IEEE set!

cheers
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Hello,

Regardless, I got this error while synthesizing a Verilog project. The
problem was that I adopted a project from ISE 7.1.04. After starting a
fresh project on ISE 9.2, handpicking the HDL files and UCFs (and so
on) the synthesis went smoothly.

Maybe this will do the trick for you too.

    Eli

On 23 Aug., 18:22, eli.billa...@gmail.com wrote:
> Regardless, I got this error while synthesizing a Verilog project. The
> problem was that I adopted a project from ISE 7.1.04. After starting a
> fresh project on ISE 9.2, handpicking the HDL files and UCFs (and so
> on) the synthesis went smoothly.

I had the problem with a fresh 9.2 VHDL-only project. Which version of
fixed_pkg did you use? The Xilinx-adapted from http://www.eda-stds.org/fphdl/vhdl.html,
or the original package from the VHDL200x website?

Thanks,
Andreas