Xilinx PACKER warning bout carry

What does this "PACKER" warning
mean?

Lut _ driving carry _ can not
be packed with the carry due
to conflict with the common
signal requirement between Lut
inputs and the Carry DI/MAND pins.
This would result in an extra Lut
for a feedthrough.

Here is the VHDL code:

 count_int_proc:process(clk)
 begin
 if(clk'event and clk='1')then
   if(reset='1')then
     count_int <= start_value;
   elsif( enable='1') then
     if(up='1' and count_int<max)then
       count_int<=count_int+1;
     elsif( down='1'and count_int>0) then
       count_int<=count_int-1;
     end if;
   end if;
 end if;
 end process;

Thanks,
Brad Smallridge
AI Vision

Are you sure you need > (greater than) operator here?
This requires a subtraction and a carry chain, so your counter needs
two carry chains and won't pack.
Can you use not-equal instead?

(This also applies to < (less than) operator)

Alan Nishioka


On Aug 14, 6:17 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
> What does this "PACKER" warning
> mean?
>
> Lut _ driving carry _ can not
> be packed with the carry due
> to conflict with the common
> signal requirement between Lut
> inputs and the Carry DI/MAND pins.
> This would result in an extra Lut
> for a feedthrough.
>
> Here is the VHDL code:
>
>  count_int_proc:process(clk)
>  begin
>  if(clk'event and clk='1')then
>    if(reset='1')then
>      count_int <= start_value;
>    elsif( enable='1') then
>      if(up='1' and count_int<max)then
>        count_int<=count_int+1;
>      elsif( down='1'and count_int>0) then
>        count_int<=count_int-1;
>      end if;
>    end if;
>  end if;
>  end process;
>
> Thanks,
> Brad Smallridge
> AI Vision

On Aug 14, 8:17 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
> What does this "PACKER" warning
> mean?
>
> Lut _ driving carry _ can not
> be packed with the carry due
> to conflict with the common
> signal requirement between Lut
> inputs and the Carry DI/MAND pins.
> This would result in an extra Lut
> for a feedthrough.
>
> Here is the VHDL code:
>
>  count_int_proc:process(clk)
>  begin
>  if(clk'event and clk='1')then
>    if(reset='1')then
>      count_int <= start_value;
>    elsif( enable='1') then
>      if(up='1' and count_int<max)then
>        count_int<=count_int+1;
>      elsif( down='1'and count_int>0) then
>        count_int<=count_int-1;
>      end if;
>    end if;
>  end if;
>  end process;
>
> Thanks,
> Brad Smallridge
> AI Vision

If you use an integer subtype for count_int and check for
"not(count_int - 1 < 0)" or "not (count_int + 1 > max)" then the carry
out of the incrementor and decrementor can be shared with the
respective comparison (and/or similarly optimized). That's also
assuming max = 2**N-1 for positive integer N. Don't try this with SLV
or UNSIGNED.

Andy

Brad Smallridge wrote:
> What does this "PACKER" warning
> mean?

The fitter feels guilty about one of the LUTs it used.
It's just a warning.
Unless I were short on LUTs I would
not spend time on it.

The code looks ok to me.
You could combine the up/down input.


      -- Mike Treseler

Thanks Alan,

if(up='1' and count_int/=max)then
...
elsif( down='1'and count_int/=0) then
...
got rid of the warnings
and a considerable numbers of slices.

The only difference I can see is that
my start_value had better be "in range"
which is OK for my aplication.

Brad

"Alan Nishioka" <alan@nishioka.com> wrote in message 
news:1187178437.624159.196390@i38g2000prf.googlegroups.com...
> Are you sure you need > (greater than) operator here?
> This requires a subtraction and a carry chain, so your counter needs
> two carry chains and won't pack.
> Can you use not-equal instead?
>
> (This also applies to < (less than) operator)
>
> Alan Nishioka
>
>
> On Aug 14, 6:17 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
> wrote:
>> What does this "PACKER" warning
>> mean?
>>
>> Lut _ driving carry _ can not
>> be packed with the carry due
>> to conflict with the common
>> signal requirement between Lut
>> inputs and the Carry DI/MAND pins.
>> This would result in an extra Lut
>> for a feedthrough.
>>
>> Here is the VHDL code:
>>
>>  count_int_proc:process(clk)
>>  begin
>>  if(clk'event and clk='1')then
>>    if(reset='1')then
>>      count_int <= start_value;
>>    elsif( enable='1') then
>>      if(up='1' and count_int<max)then
>>        count_int<=count_int+1;
>>      elsif( down='1'and count_int>0) then
>>        count_int<=count_int-1;
>>      end if;
>>    end if;
>>  end if;
>>  end process;
>>
>> Thanks,
>> Brad Smallridge
>> AI Vision
>
> 

Hi Andy,
I could see where this might save a lot of hardware by using
the carry flag, however, all my variables in my example
were std_logic_vector inputs and the max need not be 2**N-1.

Brad Smallridge

> If you use an integer subtype for count_int and check for
> "not(count_int - 1 < 0)" or "not (count_int + 1 > max)" then the carry
> out of the incrementor and decrementor can be shared with the
> respective comparison (and/or similarly optimized). That's also
> assuming max = 2**N-1 for positive integer N. Don't try this with SLV
> or UNSIGNED.
>
> Andy
> 

Thanks Mike,

I am using this code to adjust a value for a menu
display and I have pushbuttons controlling its value.
One pb for up and another for down. Having separate
up and down inputs was the first thing that occurred to
me, although that isn't usually how an up/down counter
is ported, is it. The enable is controlled by the
"cursor" position.

Brad Smallridge
Ai Vision

"Mike Treseler" <mike_treseler@comcast.net> wrote in message 
news:5ih1tfF3pv0r9U1@mid.individual.net...
> Brad Smallridge wrote:
>> What does this "PACKER" warning
>> mean?
>
> The fitter feels guilty about one of the LUTs it used.
> It's just a warning.
> Unless I were short on LUTs I would
> not spend time on it.
>
> The code looks ok to me.
> You could combine the up/down input.
>
>
>      -- Mike Treseler 

Brad Smallridge wrote:

> if(up='1' and count_int/=max)then
> ...
> elsif( down='1'and count_int/=0) then
> ...
> got rid of the warnings
> and a considerable numbers of slices.

I saw a reduction from 28 to 27 ALUTs with /=
for limits of 1 and -1+2**16 using quartus.

No warnings and 17 registers in either case.

I might keep the original description
as clearer and very slightly safer.

Interesting example.

        -- Mike Treseler

Brad Smallridge wrote:

> I am using this code to adjust a value for a menu
> display and I have pushbuttons controlling its value.
> One pb for up and another for down.

Ahh. I see. How do you debounce?

> Having separate
> up and down inputs was the first thing that occurred to
> me, although that isn't usually how an up/down counter
> is ported, is it. 

Well, two inputs is two inputs and
there aren't really any LS191's inside anyway :)

> The enable is controlled by the
> "cursor" position.

Sounds like fun.

        -- Mike Treseler

> I saw a reduction from 28 to 27 ALUTs with /=
> for limits of 1 and -1+2**16 using quartus.

I am not sure what is going on Mike. I cleaned
up my code to post here below called count_test.
Count_test has quite a few LUTs because I guess
all the inputs are variables. Count_wrap wraps
Count_test and holds max and start to constant
values, a situation that I think would be the
most likely use. Here the less/greater than
packed better than not equal. Go figure.
I then ran my top level again to see if my
original results were wrong. They were not.
The not equal version ran better. I'm thinking
that the clutter in the design may effect how
well the counters versions are synthesized.

-------------  FFlops 4inLUts Slices Warnings
count_test /=  16     65      41     15
count_wrap /=  16     32      17     0
count_wrap <>  16     30      16     0
       top /=  415    479     451
       top <>  414    535     493

There are three counters presently in top, more to
come.

Brad Smallridge
Ai Vision


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity count_test is
 port(
   clk    :  in std_logic;
   reset  :  in std_logic;
   enable :  in std_logic;
   up     :  in std_logic;
   down   :  in std_logic;
   start  :  in std_logic_vector(15 downto 0);
   max    :  in std_logic_vector(15 downto 0);
   count  : out std_logic_vector(15 downto 0) );
end count_test;

architecture beh of count_test is

 signal count_int : std_logic_vector(15 downto 0);

begin

 count_int_proc:process(clk)
 begin
 if(clk'event and clk='1')then
   if(reset='1')then
     count_int <= start;
   elsif( enable='1') then
     if( up='1' and count_int/=max )then
   --if( up='1' and count_int<max )then
       count_int<=count_int+1;
     elsif( down='1' and count_int/=0 )then
   --elsif( down='1' and count_int>0 )then
       count_int<=count_int-1;
     end if;
   end if;
 end if;
 end process;

 count_proc:process(count_int)
 begin
   count <= count_int;
 end process;

end beh;

---------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity count_wrap is
 port(
   clk    :  in std_logic;
   reset  :  in std_logic;
   enable :  in std_logic;
   up     :  in std_logic;
   down   :  in std_logic;
   count  : out std_logic_vector(15 downto 0) );
end count_wrap;

architecture beh of count_wrap is

 component count_test
 port(
   clk    :  in std_logic;
   reset  :  in std_logic;
   enable :  in std_logic;
   up     :  in std_logic;
   down   :  in std_logic;
   start  :  in std_logic_vector(15 downto 0);
   max    :  in std_logic_vector(15 downto 0);
   count  : out std_logic_vector(15 downto 0) );
 end component;

begin

 count_test_1: count_test
 port map(
   clk    => clk,
   reset  => reset,
   enable => enable,
   up     => up,
   down   => down,
   start  => "0000000000000001",
   max    => "1000000000000101",
   count  => count );

end beh;