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Spartan-3A DSP vs. Cyclone III Power-wise

Started by Manny August 21, 2007
Hi,

Well the subject says it all. Just wondering how does Spartan-3A DSP
compares to Cyclone III in terms of power efficiency. I know the
spartan is 90nm and hence should be less favourable. However, does it
by any means at least approach the power performance of the cyclone?

Thanks,
-Manny

On 21 Aug, 12:58, Manny <mlou...@hotmail.com> wrote:
> Hi, > > Well the subject says it all. Just wondering how does Spartan-3A DSP > compares to Cyclone III in terms of power efficiency. I know the > spartan is 90nm and hence should be less favourable. However, does it > by any means at least approach the power performance of the cyclone? > > Thanks, > -Manny
Hi Manny, Depends if you are working utlizing the suspend mode in Spartan3. Then at least static power will be more or less the same. For running, TSMC lowpower 65 nm will do the trick for Altera. So it all comes down to your power budget. Regards Fredrik
Manny,

Request the C3 vs S3A power comparison slides from your FAE.

To me, while running (dynamic + static), it seems to be a wash (roughly
equal, with S3A slightly better).

When not running, S3A has power savings modes, so it is a clear winner
if you decide to use one or both of the modes).

Of course, it isn't hard to create a design where one, or the other
shows an advantage for dynamic+static power.  This slide set attempts to
have a apples to apples comparison:  you judge how careful we were to
make things "the same."

In general, the 90nm node for medium performance transistors is less
leaky (less static power), and also has more dynamic power than 65nm.

65nm is generally leakier, unless performance is lessened by increasing
the Vt's of the core transistors.  In fact, at 65nm, even the gates leak
(this static current is independent of temperature).

The steepness of the increase in static current of 65nm is much greater
than at 90nm with increasing junction temperature.  Be sure to use a die
temperature that is in keeping with your real application.

Austin
First, I will disclose that I work for Altera. My advice is to try the
comparisons yourself and you will find out which family is best for
you.

Altera has made it very easy to verify power consumption claims
yourself using the Cyclone III FPGA Starter Kit. It provides an
application note and circuitry to easily measure Cyclone III FPGA
static and dynamic power consumption.
http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html.
You can also purchase the EP3C120 device for measurement using your
own board. A board including the largest Cyclone III EP3C120 is in
development.

In the interest of providing both sides of the story I will provide
some responses to the claims below.

On Aug 21, 8:12 am, austin <aus...@xilinx.com> wrote:
> Manny, > > Request the C3 vs S3A power comparison slides from your FAE. > > To me, while running (dynamic + static), it seems to be a wash (roughly > equal, with S3A slightly better).
Using the power estimator results from both vendors does not substantiate this claim. For example, looking at static power only, The Cyclone III EP3C120 has roughly 119K logic elements and 3,888 kits of memory while its static power consumption is just 0.169 whether it is active or suspended. The Xilinx XC3SD3400A has 23,872 slices which is roughly equivalent to just 48K logic elements and has 2268 kbits of memory. Static power for the low power version of this part in active mode is 0.451W. In suspend mode it drops to 0.234W while the part is suspended. These comparisons used the latest versions of both spreadsheet estimators and assume 85C junction temperature and still air.
> When not running, S3A has power savings modes, so it is a clear winner > if you decide to use one or both of the modes).
Altera devices include an ALTCLKCNTRL function that can be used to shut off clock networks to lower power consumption. Altera users are not penalized with higher static power consumption when the clocks resume operation. This function provides fine grained control over what is shut on/off and how much power savings is achieved. You can shut down the whole part or just selected functions/clocks which provides a lot of flexibility.
> Of course, it isn't hard to create a design where one, or the other > shows an advantage for dynamic+static power. This slide set attempts to > have a apples to apples comparison: you judge how careful we were to > make things "the same."
> In general, the 90nm node for medium performance transistors is less > leaky (less static power), and also has more dynamic power than 65nm. > > 65nm is generally leakier, unless performance is lessened by increasing > the Vt's of the core transistors. In fact, at 65nm, even the gates leak > (this static current is independent of temperature).
In general these statements are true if nothing is done to mitigate these issues. However, the Altera Cyclone III architecture is built on TSMC's low power process and uses an intelligent selection of low Vt's for fast performance only where speed critical. In non-speed critical circuits slower, higher Vt transistors are used. Altera also uses low Vt transistors coupled with longer channel lengths to get a balance between good performance and low leakage.
> The steepness of the increase in static current of 65nm is much greater > than at 90nm with increasing junction temperature. Be sure to use a die > temperature that is in keeping with your real application. > > Austin
The proof is in the pudding. Regardless of what Austin or I say, perform your own comparisons and I am confident you will be impressed by the combination of relatively higher performance, higher functionality, and lower power consumption Cyclone III FPGAs deliver. Regards, Rob
Many thanks all for the input.

At some stage, once I'm done with designing the system, I'll try to
gauge things in real-world and hope for the best.

Regards,
-Manny

Hi,

Rob hit most of the points I would make.  I would also refer you to
http://www.altera.com/products/devices/cyclone2/features/power/cy2-power-compare.html
-- this is our take on the Cyclone *II* vs. Spartan-3 power story.
Regardless of how much of that material you believe (it can be
independently verified with hardware from the two vendors), when you
extend this comparison to Cyclone III devices, Cyclone III will
clearly have lower power.  I'll focus on dynamic power, since Rob
didn't touch on it much.

Both chips have the same Vdd supply voltage (1.2V).  However, Cyclone
III devices are manufactured in a 65 nm process vs. a 90 nm process in
the case of Spartan-3 (and Cyclone II devices).  This results in (a) a
reduction in the linear dimensions of the chip and thus metal
capacitance, and (b) a reduction in the size of the transistors and
resulting capacitance.  Overall, this leads to a ~30% (off the top of
my head) dynamic power reduction compared to Cyclone II devices.

On top of this, the Cyclone device family has been highly optimized
for low area (e.g. cost).  One side-effect of this is that the dynamic
power for a given amount of logic tends to be lower than higher-
performance families.  On top of this, we found in Cyclone II device
vs. Spartan-3 comparisons (referenced above) that the Cyclone II
device's power was significantly lower (~1/2) than that of Spartan-3,
despite being in the same process and with the same supply voltage.

Bottom line: You should expect much lower power in Cyclone III vs.
Cyclone II (you can trust us on that!), and thus it should not be hard
to convince yourself that Cyclone III should have signficantly less
power consumption than Spartan-3 (which is harder to trust us on :-)).

Regards,

Paul Leventis
Altera Corp.

Does anyone know if Spartan 3A-DSP is based of Virtex4SX, or is
Virtex4SX?

That might explain why the power is higher.

x


Spartan 3AD is based on Spartan 3A,

Austin