Design Flow: PCI or any other high-speed PC interface ?

  I would like to accelerate a data conversion task. We just send a stream
of data to converter that produses a response stream. Actually, this
converter is an emulator of a system we are going to simulate efficiently
accelerating simulation task. As the goal is a number of simulations per
time unit, the high performance channels are needed to communicate between
application running on PC and emulator running on FPGA. The data conversion
(encription, compression) should be a known and well-understood toipc; thus,
I would like to see any good reference designs.
  As, I do not have any experiance in high-speed I/O, I would like to
discover existing and popular high speed interfaces (DRIVERS, tools,
examples, defign flows, methodologies, cores, etc.). Can anybody offer an
Internet resource or an exellent book describing the topic? How many time
would it take to built a simplest prototype in man-hours (100, 1000,
million)? How costly will it be?

 Many thanks.

In article <bvnv15$uhbvk$1@ID-212430.news.uni-berlin.de>, 
valentin_NOSPAM_NOWORMS@abelectron.com says...
>   I would like to accelerate a data conversion task. We just send a stream
> of data to converter that produses a response stream. Actually, this
> converter is an emulator of a system we are going to simulate efficiently
> accelerating simulation task. As the goal is a number of simulations per
> time unit, the high performance channels are needed to communicate between
> application running on PC and emulator running on FPGA. The data conversion
> (encription, compression) should be a known and well-understood toipc; thus,
> I would like to see any good reference designs.
>   As, I do not have any experiance in high-speed I/O, I would like to
> discover existing and popular high speed interfaces (DRIVERS, tools,
> examples, defign flows, methodologies, cores, etc.). Can anybody offer an
> Internet resource or an exellent book describing the topic? How many time
> would it take to built a simplest prototype in man-hours (100, 1000,
> million)? How costly will it be?

A million oughta cover it. ;-)


The various FPGA manufacturers have PCI cores, and such, for their 
products, but I've found them expensive in terms of up-front $$ and 
FPGA space.  I decided to go with a PLX PCI-9054 (kinda long in the 
tooth now) as a PCI bridge.  Drivers were readily available for it.

See: http://www.plxtech.com/  You'll have to register to get the 
detailed specs (why, I haven't a clue). 

For more general information, try: 

http://www.opencores.org/   <== "open hardware" cores
http://www.optimagic.com/   <== programmable logic jump station

-- 
  Keith

Valentin,

You need to be more specific in terms of what speeds you want to achieve,
whether the rate has to be sustained, what kind of compression/encryption,
etc... ?

/Mikhail

-- 
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")





"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:bvnv15$uhbvk$1@ID-212430.news.uni-berlin.de...
>   I would like to accelerate a data conversion task. We just send a stream
> of data to converter that produses a response stream. Actually, this
> converter is an emulator of a system we are going to simulate efficiently
> accelerating simulation task. As the goal is a number of simulations per
> time unit, the high performance channels are needed to communicate between
> application running on PC and emulator running on FPGA. The data
conversion
> (encription, compression) should be a known and well-understood toipc;
thus,
> I would like to see any good reference designs.
>   As, I do not have any experiance in high-speed I/O, I would like to
> discover existing and popular high speed interfaces (DRIVERS, tools,
> examples, defign flows, methodologies, cores, etc.). Can anybody offer an
> Internet resource or an exellent book describing the topic? How many time
> would it take to built a simplest prototype in man-hours (100, 1000,
> million)? How costly will it be?
>
>  Many thanks.
>
>

I'm trying to be very specific telling that the target application is
simulations accelerator. The higher speed the better. As converter will be
running on FPGA, this limits number of vectors per second that can be
simulated to about 200MHz. Hence, the desired bandwidth is
number_of_vectors_per_second * vector_width gives about 100Mbps..10Gbps (for
both channels). Channels should not be symmetric (input can be faster than
output or vice versa). I just want to discover existing PC-interfacing
solutions, make a broader view in the field.

Rather than doing conversion task in SW it is often more desirable to use a
task specific HW. All kinds of FPGA-based accelerators are becoming more and
more popular. I've even seen about universal FPGA-accelerators. Data
converter is a simplest accelerator; its communication scheme includes only
one input and one output stream. The simulator I would like to implement
belogns to data conversion class as well.  I have mentioned
compression/encription asking for typical reference design of data
converter. Thanks.

If you want your emulator to be pluggable into a standard PC, then the most
obvious choice for the interface is PCI. With standard 32 bit 33 MHz PCI you
can theoretically achieve 132 MByte/s. In practice I have achieved over 100
MByte/s. If this is not enough you can go to 64 bit / 66 MHz PCI, which is
pretty common nowadays too. To achieve high speeds on PCI bus your emulator
would have to be a bus master for both reads and writes. The next step in
performance is PCI-X, but I don't think it is wide spread among PC
motherboards...

Another way is to make your card look like a memory module. I think this
approach was discussed here in the past. This seems like an interesting
idea, but personally I prefer staying with standard interfaces.

Then there are all kinds of fast serial buses, but if I were you I wouldn't
go there for this application.


/Mikhail

-- 
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")



"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:bvqnq5$vmk1b$1@ID-212430.news.uni-berlin.de...
> I'm trying to be very specific telling that the target application is
> simulations accelerator. The higher speed the better. As converter will be
> running on FPGA, this limits number of vectors per second that can be
> simulated to about 200MHz. Hence, the desired bandwidth is
> number_of_vectors_per_second * vector_width gives about 100Mbps..10Gbps
(for
> both channels). Channels should not be symmetric (input can be faster than
> output or vice versa). I just want to discover existing PC-interfacing
> solutions, make a broader view in the field.
>
> Rather than doing conversion task in SW it is often more desirable to use
a
> task specific HW. All kinds of FPGA-based accelerators are becoming more
and
> more popular. I've even seen about universal FPGA-accelerators. Data
> converter is a simplest accelerator; its communication scheme includes
only
> one input and one output stream. The simulator I would like to implement
> belogns to data conversion class as well.  I have mentioned
> compression/encription asking for typical reference design of data
> converter. Thanks.
>
>

In comp.arch.fpga valentin tihomirov <valentin_NOSPAM_NOWORMS@abelectron.com> wrote:
:   I would like to accelerate a data conversion task. We just send a stream
: of data to converter that produses a response stream. Actually, this
: converter is an emulator of a system we are going to simulate efficiently
: accelerating simulation task. As the goal is a number of simulations per
: time unit, the high performance channels are needed to communicate between
: application running on PC and emulator running on FPGA. The data conversion
: (encription, compression) should be a known and well-understood toipc; thus,
: I would like to see any good reference designs.
:   As, I do not have any experiance in high-speed I/O, I would like to
: discover existing and popular high speed interfaces (DRIVERS, tools,
: examples, defign flows, methodologies, cores, etc.). Can anybody offer an
: Internet resource or an exellent book describing the topic? How many time
: would it take to built a simplest prototype in man-hours (100, 1000,
: million)? How costly will it be?

If you only need to send data between some peripheral and the PC and latency
isn't an issue, think about using a USB2 link, like the usrp Software radio
peripheral (http://comsec.com/wiki?UsrpProtoIntro) does. About 32 MByte/sec
were reached with unidirectional flow, 16 MByte in each direction
bidirectional and a complete chain is provided.

That way, you don't need to design an PCI adapter and can easily plug into
any modern PC without opening it.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

"MM" <mbmsv@yahoo.com> wrote in message
news:bvr63s$vm2au$1@ID-204311.news.uni-berlin.de...
> If you want your emulator to be pluggable into a standard PC, then the
most
> obvious choice for the interface is PCI. With standard 32 bit 33 MHz PCI
you
> can theoretically achieve 132 MByte/s. In practice I have achieved over
100
> MByte/s. If this is not enough you can go to 64 bit / 66 MHz PCI, which is
> pretty common nowadays too. To achieve high speeds on PCI bus your
emulator
> would have to be a bus master for both reads and writes. The next step in
> performance is PCI-X, but I don't think it is wide spread among PC
> motherboards...
>
> Another way is to make your card look like a memory module. I think this
> approach was discussed here in the past. This seems like an interesting
> idea, but personally I prefer staying with standard interfaces.
>
> Then there are all kinds of fast serial buses, but if I were you I
wouldn't
> go there for this application.

Thank you, Mihail. I'm aware about these opportunities and would like to
know more. Looking for overviews, tools and step-by-step methodologies.

On Wed, 04 Feb 2004 14:16:29 +0200, valentin tihomirov wrote:

> I'm trying to be very specific telling that the target application is
> simulations accelerator. The higher speed the better. As converter will be
> running on FPGA, this limits number of vectors per second that can be
> simulated to about 200MHz. Hence, the desired bandwidth is
> number_of_vectors_per_second * vector_width gives about 100Mbps..10Gbps (for
> both channels). Channels should not be symmetric (input can be faster than
> output or vice versa). I just want to discover existing PC-interfacing
> solutions, make a broader view in the field.
> 
> Rather than doing conversion task in SW it is often more desirable to use a
> task specific HW. All kinds of FPGA-based accelerators are becoming more and
> more popular. I've even seen about universal FPGA-accelerators. Data
> converter is a simplest accelerator; its communication scheme includes only
> one input and one output stream. The simulator I would like to implement
> belogns to data conversion class as well.  I have mentioned
> compression/encription asking for typical reference design of data
> converter. Thanks.

10 Gbps is pretty fast. The only way to get data in or out of a PC at that
speed is to use the memory bus.

Typical PCI is a little over 1 Gbps (theoretical). If you go 64-bit 66
MHz PCI, that is only 4 times faster at 4 Gbps. Maybe PCI-X is fast
enough for you. If you are using an FPGA, why don't you see if the FPGA
vendor can fix you up with a 133 MHz PCI-X core?

Good luck!

Mac

I have found the example at:

http://sise.ttu.ee/users/nalle/etf99/annotation.html

The most interesting thing is that it is my university teacher's project.

valentin tihomirov wrote:

 >   I would like to accelerate a data conversion task. We just send a stream
 > of data to converter that produses a response stream. Actually, this
 > converter is an emulator of a system we are going to simulate efficiently
 > accelerating simulation task. As the goal is a number of simulations per
 > time unit, the high performance channels are needed to communicate between
 > application running on PC and emulator running on FPGA.


Consider 100/1000 Ethernet.

    -- Mike Treseler