Hi, I am confused about the clocking scheme of the two most popular hdl. The most common usage of clock and reset signal is clk'event clk=3D1 or reset=3D1. As you see reset signal seem to be a level sensitive as it should be. But in verilog the common structure for clocking is posedge clk or negedge reset. As you see there is an edge constraint for reset signal in verilog. Why this is different in these hdls. Does this have any importance from the technology point of view ? I mean if the synthesized circuits are same or different by the same synthesis tool. An=FDl =C7ELEB=DD
VHDL clocking scheme VS Verilog clocking scheme
Started by ●August 28, 2007
Reply by ●August 28, 20072007-08-28
On Tue, 28 Aug 2007 01:40:22 -0700, anilcelebi@gmail.com wrote:>Hi, > >I am confused about the clocking scheme of the two most popular hdl. >The most common usage of clock and reset signal is clk'event clk=1 or >reset=1.I hope you are now using the much clearer form rising_edge(clock) but yes, you're right.>As you see reset signal seem to be a level sensitive as it >should be. But in verilog the common structure for clocking is posedge >clk or negedge reset. As you see there is an edge constraint for reset >signal in verilog. Why this is different in these hdls.Because Verilog cannot detect the clock edge in procedural code. Many people are surprised to see the edge specification on reset in Verilog. However, think what would happen without it.... always @((posedge clock) or reset) /// WRONG if (reset == 1'b0) Q <= 0; else Q <= D; Imagine that clock is frozen at 0. Now make reset go from 1 to 0: this is good, the edge on reset triggers the always block, (reset==1'b0) is true, the flip-flop resets. Next, take reset away (0->1). The rising edge on reset will again trigger the always block. (reset==1'b0) is now false. Consequently, the clocked action Q<=D is executed. This is clearly wrong.> Does this have >any importance from the technology point of view ? I mean if the >synthesized circuits are same or different by the same synthesis tool.No. Synthesis treats the standard clocked templates in the same way for Verilog and VHDL. The one big difference is that it is effectively impossible to use this style in Verilog to describe a flip-flop that has BOTH asynchronous set AND asynchronous reset, whereas in VHDL it's easy. In practice, though, this isn't a significant problem. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●August 28, 20072007-08-28
On Aug 28, 4:54 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:> On Tue, 28 Aug 2007 01:40:22 -0700, anilcel...@gmail.com wrote: > >Hi, > > >I am confused about the clocking scheme of the two most popular hdl. > >The most common usage of clock and reset signal is clk'event clk=1 or > >reset=1. > > I hope you are now using the much clearer form > rising_edge(clock) > but yes, you're right. > > >As you see reset signal seem to be a level sensitive as it > >should be. But in verilog the common structure for clocking is posedge > >clk or negedge reset. As you see there is an edge constraint for reset > >signal in verilog. Why this is different in these hdls. > > Because Verilog cannot detect the clock edge in procedural code. > > Many people are surprised to see the edge specification on reset > in Verilog. However, think what would happen without it.... > > always @((posedge clock) or reset) /// WRONG > if (reset == 1'b0) > Q <= 0; > else > Q <= D; > > Imagine that clock is frozen at 0. Now make reset go from > 1 to 0: this is good, the edge on reset triggers the always > block, (reset==1'b0) is true, the flip-flop resets. Next, > take reset away (0->1). The rising edge on reset will > again trigger the always block. (reset==1'b0) is now false. > Consequently, the clocked action Q<=D is executed. This is > clearly wrong. >The big difference between the Verilog and VHDL template is the lack of an "if" along with the "else". In the case of clock frozen at 0, you might be able to fix this using else if (clock) but then you'd have bad behavior in the clock frozen high case. In non-synthesizable code you could add @(posedge clock) in the else clause, but that would require waiting for an additional clock edge when the always block is triggered by the rising edge of clock.> > Does this have > >any importance from the technology point of view ? I mean if the > >synthesized circuits are same or different by the same synthesis tool. > > No. Synthesis treats the standard clocked templates in the same > way for Verilog and VHDL. > > The one big difference is that it is effectively impossible to > use this style in Verilog to describe a flip-flop that has BOTH > asynchronous set AND asynchronous reset, whereas in VHDL it's > easy. In practice, though, this isn't a significant problem.What about? always @(posedge clock or negedge reset_n or negedge set_n) if (!reset_n) Q <= 0; else if (!set_n) Q <= 1; else Q <= D;> -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.
Reply by ●August 28, 20072007-08-28
On Tue, 28 Aug 2007 06:00:09 -0700, Gabor <gabor@alacron.com> wrote:>On Aug 28, 4:54 am, Jonathan Bromley wrote:>> [...] it is effectively impossible to >> use this style in Verilog to describe a flip-flop that has BOTH >> asynchronous set AND asynchronous reset, whereas in VHDL it's >> easy. In practice, though, this isn't a significant problem. > >What about? > >always @(posedge clock or negedge reset_n or negedge set_n) >if (!reset_n) > Q <= 0; >else if (!set_n) > Q <= 1; >else > Q <= D;No, that doesn't work correctly. Consider what happens if both reset_n and set_n are asserted (low) - then, of course, Q has been driven to 0. Now imagine that the high priority asynch signal, reset_n, is released back to 1. The always block does NOT trigger. Consequently, the asynchronous set - which should then take over, since it is still asserted - has no effect. You can fix that for simulation by hacking the sensitivity list: always @(posedge clock or negedge reset_n or negedge (set_n || (!reset_n)) )... but synthesis tools won't accept that because they won't accept any expression in a neg/posedge. It's a mess. Worse still, some synthesis tools accept the style you suggested and infer asynch set and reset from it, immediately generating a simulation/synthesis mismatch. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
