Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?

I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA
from Actel with IGLOO power calculator (posted on Actel website). I
received very astonishing results. With full logic utilization at 50
MHz, 25% toggle rate and around 100 I/Os (LVCMOS 1.8V, LVCMOS 3.3V) it
consumes around 100 mW. It's about half of Xilinx Coolrunner-II
consumption and a small fraction of Xilinx FPGAs (Spartan or Virtex)
for same functionality. I was very surprised by this so maybe I'm
missing something here. Is anybody familiar with this chip and its
power consumption?

On Sep 3, 7:59 pm, iko...@alumni.technion.ac.il wrote:
> It's about half of Xilinx Coolrunner-II
> consumption and a small fraction of Xilinx FPGAs (Spartan or Virtex)
> for same functionality.

Which Xilinx parts you used as a comparison point? I don't have
expertise on Actel parts, but they seem to have 'quite' optimistic
marketing gates readings, so comparing 250k part to 250k part might
not be fair.

On a related topic - does anyone have expertise about the trade-offs
of Actel's "Versa-Tiles" vs. 4/6-LUTs. It seems like obviously
wastefull configuration - how many thansistors they can really share
between 3-LUT and D-FF? Is there some benefit in this configuration,
or is this 'design choice' made just to avoid Altera and Xilinx
patents?

- Doug

<ikogan@alumni.technion.ac.il> wrote in message 
news:1188838781.893882.166580@r29g2000hsg.googlegroups.com...
>I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA
> from Actel with IGLOO power calculator (posted on Actel website). I
> received very astonishing results. With full logic utilization at 50
> MHz, 25% toggle rate and around 100 I/Os (LVCMOS 1.8V, LVCMOS 3.3V) it
> consumes around 100 mW. It's about half of Xilinx Coolrunner-II
> consumption and a small fraction of Xilinx FPGAs (Spartan or Virtex)
> for same functionality. I was very surprised by this so maybe I'm
> missing something here. Is anybody familiar with this chip and its
> power consumption?
>

I'm using IGLOO now for exactly the reasons you state. The main difference 
vs. SRAM-based FPGAs is the insanely low static current (measured in uW even 
in the largest device in the family). The dynamic current is on the order of 
30-40% vs. those guys from what I've seen. As a test I compiled a real 
design into a Xilinx XC2V250 and an AGL600V2. These devices are roughly 
comparable in size. I then and used the vendor tools to estimate power on 
the placed and routed designs. Here's what I got:

XC2V250-4CS144:

Max clock frequency: 119MHz
Flip flops: 757/3072 (24%)
4-input LUTs: 817/3072 (26%)
Block RAMs: 5/24
Estimated power: 253mW* (using Xilinx's XPower tool)
  Static: 32mW
  Dynamic: 221mW

* Calculated at 80MHz with 12.5% data toggle rate.


AGL600V2-FG144:

Max clock frequency: 33.3MHz
Flip flops: 870
Total VersaTiles: 4974/13824 (36%)
Block RAMs: 5/24
Estimated power: 66mW** (using Actel's SmartPower tool)
  Static: 0.067mW (67uW)
  Dynamic: 66mW

** Calculated at 80MHz with 12.5% data toggle rate (even though design won't 
run that fast).

The IGLOO power is ~25% of the Xilinx power at the same frequency, and the 
IGLOO static power is only 67 uW (~1/500th of the Xilinx). Truly amazing. 
You pay the price for that low power, though, as the design runs 3.5x as 
fast in the Xilinx. But for some designs, like the one I'm working on now, 
low power is paramount.

As for the Coolrunner-II, the Coolrunner is a 1.8V part vs. 1.2V for the 
IGLOO V2. That's a 50% power difference right off the bat. The rest must 
just be differences in the design and process.

Rob 

"Douglas" <j.d.morrison@gmail.com> wrote in message 
news:1189491208.142555.102930@50g2000hsm.googlegroups.com...
> On Sep 3, 7:59 pm, iko...@alumni.technion.ac.il wrote:
>> It's about half of Xilinx Coolrunner-II
>> consumption and a small fraction of Xilinx FPGAs (Spartan or Virtex)
>> for same functionality.
>
> Which Xilinx parts you used as a comparison point? I don't have
> expertise on Actel parts, but they seem to have 'quite' optimistic
> marketing gates readings, so comparing 250k part to 250k part might
> not be fair.
>
> On a related topic - does anyone have expertise about the trade-offs
> of Actel's "Versa-Tiles" vs. 4/6-LUTs. It seems like obviously
> wastefull configuration - how many thansistors they can really share
> between 3-LUT and D-FF? Is there some benefit in this configuration,
> or is this 'design choice' made just to avoid Altera and Xilinx
> patents?
>
> - Doug
>

I don't see it as wasteful. It's just a more granular and generic 
architecture, which has some advantages. I would guess that lowering power 
was also a big part of the equation. No idea about patent concerns.

Rob 

robj schrieb:
> <ikogan@alumni.technion.ac.il> wrote in message 
> news:1188838781.893882.166580@r29g2000hsg.googlegroups.com...
>> I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA
>> from Actel with IGLOO power calculator (posted on Actel website). I
>> received very astonishing results. With full logic utilization at 50
>> MHz, 25% toggle rate and around 100 I/Os (LVCMOS 1.8V, LVCMOS 3.3V) it
>> consumes around 100 mW. It's about half of Xilinx Coolrunner-II
>> consumption and a small fraction of Xilinx FPGAs (Spartan or Virtex)
>> for same functionality. I was very surprised by this so maybe I'm
>> missing something here. Is anybody familiar with this chip and its
>> power consumption?

> As for the Coolrunner-II, the Coolrunner is a 1.8V part vs. 1.2V for the 
> IGLOO V2. That's a 50% power difference right off the bat. The rest must 
> just be differences in the design and process.

The voltage counts quadratic for the power consumption. So a difference
from 1.8V to 1.2V results in a power reduction by a factor of 2.25 and
not 1.5!

Matthias

> I'm using IGLOO now for exactly the reasons you state. The main difference vs. SRAM-based FPGAs is 
> the insanely low static current.....

...and performance.


> XC2V250-4CS144:
> Max clock frequency: 119MHz

> AGL600V2-FG144:
> Max clock frequency: 33.3MHz


I got bitten recently trying to convert a design from a Cyclone I to
an Actel ProAsic3.

It was runing at 66MHz in the Cyclone I with reasonably tight IO
requirements, this took a wee bit of tweaking in Quartus but I
got it to build cleanly fairly quickly. I've no doubt I could have
translated the design to a Spartan-3 fairly quickly/easily.

After a great deal of work and some assistance from an Actel rep
I still wasn't able to get the design working in the ProAsic3,
I had naievly presumed the performance would be roughly similar
to the Altera/Xilinx parts. My get out was that my client had
chosen the part.

They're great for what they do well but just be wary if you need
to push the performance (at all).


Nial.

On Jan 16, 12:50=A0pm, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > I'm using IGLOO now for exactly the reasons you state. The main differe=
nce vs. SRAM-based FPGAs is
> > the insanely low static current.....
>
> ...and performance.
>
> > XC2V250-4CS144:
> > Max clock frequency: 119MHz
> > AGL600V2-FG144:
> > Max clock frequency: 33.3MHz
>
> I got bitten recently trying to convert a design from a Cyclone I to
> an Actel ProAsic3.
>
> It was runing at 66MHz in the Cyclone I with reasonably tight IO
> requirements, this took a wee bit of tweaking in Quartus but I
> got it to build cleanly fairly quickly. I've no doubt I could have
> translated the design to a Spartan-3 fairly quickly/easily.
>
> After a great deal of work and some assistance from an Actel rep
> I still wasn't able to get the design working in the ProAsic3,
> I had naievly presumed the performance would be roughly similar
> to the Altera/Xilinx parts. My get out was that my client had
> chosen the part.
>
> They're great for what they do well but just be wary if you need
> to push the performance (at all).
>
> Nial.

Hi Nial,

i could have saved you the trouble, i guess.
after having an almost year long struggle while converting from Xilinx
to A3P060
with a project with NO timing issues at all, well if you had timing
tweaking
requirements with Cyclone, my thumb advice would have been, DO NOT
DARE
to try the same with A3P

well, but they are OK, for what they work, nothing agains them, just
you need to know where to use them, and where not.

world first FPGA-Stamps are made of A3P060-CN132 :)

Antti

On Jan 16, 5:50=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > I'm using IGLOO now for exactly the reasons you state. The main differe=
nce vs. SRAM-based FPGAs is
> > the insanely low static current.....
>
> ...and performance.
>
> > XC2V250-4CS144:
> > Max clock frequency: 119MHz
> > AGL600V2-FG144:
> > Max clock frequency: 33.3MHz
>
> I got bitten recently trying to convert a design from a Cyclone I to
> an Actel ProAsic3.
>
> It was runing at 66MHz in the Cyclone I with reasonably tight IO
> requirements, this took a wee bit of tweaking in Quartus but I
> got it to build cleanly fairly quickly. I've no doubt I could have
> translated the design to a Spartan-3 fairly quickly/easily.
>
> After a great deal of work and some assistance from an Actel rep
> I still wasn't able to get the design working in the ProAsic3,
> I had naievly presumed the performance would be roughly similar
> to the Altera/Xilinx parts. My get out was that my client had
> chosen the part.
>
> They're great for what they do well but just be wary if you need
> to push the performance (at all).
>
> Nial.

Igloo is slow, that's true, but ProAsic3 should be able to handle 66
Mhz.  My current ProAsic3 is running at 160 Mhz, using vanilla vhdl.
No special constraints or manually placed logic blocks were needed
other than specifying clock speed.

"Matthias Alles" <REMOVEallesCAPITALS@NOeit.SPAMuni-kl.de> wrote in message 
news:gkpdq5$f02$1@news.uni-kl.de...
>
> The voltage counts quadratic for the power consumption. So a difference
> from 1.8V to 1.2V results in a power reduction by a factor of 2.25 and
> not 1.5!
>
> Matthias

Good point! 

On Jan 15, 9:15=A0pm, "robj" <r...@abc.net> wrote:
> <iko...@alumni.technion.ac.il> wrote in message
>
> news:1188838781.893882.166580@r29g2000hsg.googlegroups.com...
>
> >I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA
> > from Actel with IGLOO power calculator (posted on Actel website). I
> > received very astonishing results.

[... snip ...]

From previous experience, be very skeptical in the answers provided by
the power "estimators".  I haven't tried the Actel estimator so theirs
might be quite good.  The Xilinx estimator, at least is 9.1i, seems to
be overly pessimistic (the acutal power measured in system was about
40% lower).

>
> I'm using IGLOO now for exactly the reasons you state. The main differenc=
e
> vs. SRAM-based FPGAs is the insanely low static current (measured in uW e=
ven
> in the largest device in the family). The dynamic current is on the order=
 of
> 30-40% vs. those guys from what I've seen. As a test I compiled a real
> design into a Xilinx XC2V250 and an AGL600V2. These devices are roughly
> comparable in size. I then and used the vendor tools to estimate power on
> the placed and routed designs. Here's what I got:
>
> XC2V250-4CS144:
>
> Max clock frequency: 119MHz
> Flip flops: 757/3072 (24%)
> 4-input LUTs: 817/3072 (26%)
> Block RAMs: 5/24
> Estimated power: 253mW* (using Xilinx's XPower tool)
> =A0 Static: 32mW
> =A0 Dynamic: 221mW
>
> * Calculated at 80MHz with 12.5% data toggle rate.
>
> AGL600V2-FG144:
>
> Max clock frequency: 33.3MHz
> Flip flops: 870
> Total VersaTiles: 4974/13824 (36%)
> Block RAMs: 5/24
> Estimated power: 66mW** (using Actel's SmartPower tool)
> =A0 Static: 0.067mW (67uW)
> =A0 Dynamic: 66mW
>
> ** Calculated at 80MHz with 12.5% data toggle rate (even though design wo=
n't
> run that fast).
>
> The IGLOO power is ~25% of the Xilinx power at the same frequency, and th=
e
> IGLOO static power is only 67 uW (~1/500th of the Xilinx). Truly amazing.
> You pay the price for that low power, though, as the design runs 3.5x as
> fast in the Xilinx. But for some designs, like the one I'm working on now=
,
> low power is paramount.

Again, be careful comparing power estimators.  Both are just an
approximation of the real design unless you do much more careful
analysis.  It's difficult to compare one broad side of a barn against
another.

That said, Igloo certain has much better static power than many other
FPGAs.

BTW, if you're looking for low power, also check out the SiliconBlue
iCE65 FPGA family.  After years of working with other FPGAs, I thought
I blew a fuse on my bench supply until I realized that the SiliconBlue
FPGA was only using 27 uA of static current (measured with a much
better quality meter).  The built-in analog meter on the supply looked
like it was pegged at 0 current.  The SiliconBlue parts also have very
low dynamic power, much lower than Spartan-3A or Cyclone III parts but
aren't as fast.  All three families use a 1.2V supply.  The
SiliconBlue parts also supposedly support 1.0V, which will reduce
power consumption even more, although I haven't tried that yet.

> As for the Coolrunner-II, the Coolrunner is a 1.8V part vs. 1.2V for the
> IGLOO V2. That's a 50% power difference right off the bat. The rest must
> just be differences in the design and process.

Actually, the dynamic power is related to the square of the voltages
(fCV^2).  If I'm doing my math correctly (a dangerous thing on a
weekend), then the 1.2V parts should use about 44% less dynamic power,
or less than half the dynamic power of the 1.8V part.
(1.2V^2/1.8V^2).

Steve Knapp
Prevailing Technology, Inc.
www.prevailing-technology.com